Results 21 to 30 of about 381 (171)
Journal of Physics: Conference Series, 2022 Abstract Results of laser-induced single event upset testing of devices with embedded error correction codes are described. Specifically, the memory system, consisting of a Micron MT41K256M16TW-107 IT: P 32 Meg×16×8 banks Dual Dynamic Random Access Memories (DDRs) was tested on a self-made test board. Two samples of each memory system or
Yang Han +4 more
openaire +1 more source
A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test
IEEE Access, 2020 Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits.
Zhangqing He +5 more
doaj +1 more source
A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture [PDF]
, 2023 The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability.
Akoglu, Ali +2 more
core +1 more source
Efficient implementation of error correction codes in hash tables [PDF]
, 2014 Hash tables are one of the most commonly used data structures in computing applications. They are used for example to organize a data set such that searches can be performed efficiently.
Maestro, J. A. +9 more
core +1 more source
Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes [PDF]
, 2021 As technology scales, radiation induced soft errors create more complex error patterns in memories with a single particle corrupting several bits. This poses a challenge to the Error Correction Codes (ECCs) traditionally used to protect memories that can
Xiao, Liyi +3 more
core +1 more source
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction [PDF]
, 2014 Static random access memories (SRAMs) are key in electronic systems. They are used not only as standalone devices, but also embedded in application specific integrated circuits.
Pontarelli, Salvatore +5 more
core +1 more source
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation
IEEE Access, 2016 Wireless communication at near-capacity transmission throughputs is facilitated by employing sophisticated Error Correction Codes (ECCs), such as turbo codes.
Ra'ed Al-Dujaily +5 more
doaj +1 more source
Error correction through language processing [PDF]
, 2015 There are two fundamental approaches for error correction. One approach is to add external redundancy to data. The other approach is to use the redundancy inside data, even if it is only the residual redundancy after a data compression algorithm.
Bruck, Jehoshua +5 more
core +1 more source
Multiple Cell Upsets Correction for OLS Codes [PDF]
, 2020 : An Error Correction code with Parity check matrix is implemented which is other type of the One Step Majority Logic Decodable (OS-MLD) called as Orthogonal Latin Squares (OLS) codes.
core
Reliability of Error Correction Codes Against Multiple Events by Accumulation [PDF]
, 2023 Modern nanoscale devices with storage capacity typically implement error correction codes (ECCs) in order to cope with the effects of natural radiation.
Franco Peláez, Francisco Javier +2 more
core