FLARES: an aging aware algorithm to autonomously adapt the error correction capability in NAND Flash memories [PDF]
, 2014 With the advent of solid-state storage systems, NAND flash memories are becoming a key storage technology. However, they suffer from serious reliability and endurance issues during the operating lifetime that can be handled by the use of appropriate ...
Bertozzi, D. +6 more
core +1 more source
Binary Biometrics: An Analytic Framework to Estimate the Performance Curves Under Gaussian Assumption [PDF]
, 2010 In recent years, the protection of biometric data has gained increased interest from the scientific community. Methods such as the fuzzy commitment scheme, helper-data system, fuzzy extractors, fuzzy vault, and cancelable biometrics have been proposed ...
Breebaart, Jeroen +5 more
core +8 more sources
Fault-tolerance techniques for hybrid CMOS/nanoarchitecture [PDF]
, 2010 The authors propose two fault-tolerance techniques for hybrid CMOS/nanoarchitecture implementing logic functions as look-up tables. The authors compare the efficiency of the proposed techniques with recently reported methods that use single coding ...
A. Melouki +24 more
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Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory
IEEE Access, 2019 With the fast development of non-volatile storage technology, NAND flash memory faces more and more challenges such as data reliability and lifetime. To overcome the issue of the reliability, low-density parity-check (LDPC) codes are considered as a main
Xingcheng Liu, Guojun Yang, Xuechen Chen
doaj +1 more source
A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test
IEEE Access, 2020 Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits.
Zhangqing He +5 more
doaj +1 more source
EDACs and test integration strategies for NAND flash memories [PDF]
, 2010 Mission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device
Michele Fabiano +8 more
core +2 more sources
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2020 Multilevel cell (MLC) memories have been advocated for increasing density at low cost in next generation memories. However, the feature of several bits in a cell reduces the distance between levels; this reduced margin makes such memories more vulnerable
Shanshan Liu, P. Reviriego, F. Lombardi
semanticscholar +1 more source
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation
IEEE Access, 2016 Wireless communication at near-capacity transmission throughputs is facilitated by employing sophisticated Error Correction Codes (ECCs), such as turbo codes.
Ra'ed Al-Dujaily +5 more
doaj +1 more source
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018 Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments.
J. Gracia-Morán +3 more
semanticscholar +1 more source
Comparison of channel coding schemes for molecular communications systems [PDF]
, 2015 Future applications for nano-machines, such as drug-delivery and health monitoring, will require robust communications and nanonetworking capabilities. This is likely to be enabled via the use of molecules, as opposed to electromagnetic waves, acting as ...
Higgins, Matthew D. +2 more
core +1 more source