Results 11 to 20 of about 2,524 (188)
ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation
IEEE Journal of the Electron Devices Society, 2021 Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs.
Mengfu Di +3 more
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Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network
IEEE Journal of the Electron Devices Society, 2021 Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which ...
Mengfu Di +3 more
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IEEE Journal of the Electron Devices Society, 2023 The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by
Yi-Chun Huang, Ming-Dou Ker
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TCAD Simulation Study of ESD Behavior of InGaAs/InP Heterojunction Tunnel FETs
Crystals, 2020 For the first time, we investigated the electrostatic discharge (ESD) behavior of an InGaAs/InP heterojunction tunneling field effect transistor (HTFET). The device structure in this study has a high on-state current without extra process steps.
Zhihua Zhu +5 more
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Analyze Scalable Sudoku-Type DTSCR ESD Protection Array Structures in 22nm FDSOI
IEEE Journal of the Electron Devices Society, 2021 This paper reports the design and analysis of scalable Sudoku-type diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharge (ESD) protection structures fabricated in a foundry 22nm fully-depleted silicon-on-insulator (FDSOI ...
Cheng Li +5 more
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Pad-Based CDM ESD Protection Methods Are Faulty
IEEE Journal of the Electron Devices Society, 2020 Charged device model (CDM) electrostatic discharge (ESD) protection remains a huge challenge for integrated circuit (IC) reliability designs. The “internal-oriented” CDM model and the “external-oriented” human body model (HBM)
Mengfu Di +3 more
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3D TCAD Analysis Enabling ESD Layout Design Optimization
IEEE Journal of the Electron Devices Society, 2020 On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which
Zijin Pan +4 more
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IEEE Journal of the Electron Devices Society, 2021 This paper presents the first co-design analysis of 28GHz broadband single-pole double-throw (SPDT) distributed travelling wave RF switches implemented in a foundry 22nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology, featuring 9KV full-chip
Mengfu Di +5 more
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IEEE Access, 2023 The modern electronic device should be able to provide stable voltage and current under a variety of conditions. The LDO regulator used in the electronic device is a system that requires various voltages and load currents.
Sang-Wook Kwon, Yong-Seo Koo
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IEEE Journal of the Electron Devices Society, 2021 4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide
Kyoung-Il Do +3 more
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