Results 41 to 50 of about 1,658 (201)
Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching
Dynamically and partially reconfigurable Field Programmable Gate Arrays (FPGAs) offer high performances and flexibility. These platforms can hot-swap reconfigurable regions to change the hardware behavior at the cost of a reconfiguration process.
Alexis Duhamel, Sebastien Pillement
doaj +1 more source
Resource-Aware Task Scheduling and Placement in Multi-FPGA System
With the development of high performance computing, Field Programmable Gate Arrays (FPGAs) are widely used for task acceleration. Partial reconfigurable technology provides the possibility of multi-task concurrent computation on FPGAs.
Zichang Sun, Haitao Zhang, Zehan Zhang
doaj +1 more source
Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs) [PDF]
Abstract This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is ...
Segreen Ingersoll, Sotirios G. Ziavras
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This paper reviews the physics of liquid metals in RF devices, including the influence of mechanical strain on resonance as well as fabrication methods and strategies for designing tunable and strain‐tolerant inductors, capacitors, and antennas.
Md Saifur Rahman, William J. Scheideler
wiley +1 more source
Conducting functional control of field-programmable gate arrays
Approaches to accomplishing functional control of field-programmable gate arrays (FPGA) are described. The first part of the article describes the existing equipment that allows conducting functional tests of FPGAs.
A. A. Ogurtsov
doaj +1 more source
Scalable Hydrodynamics on multiple Field-Programmable Gate Arrays (FPGAs)
This paper presents scalable 2D and 3D Hydrodynamics solver implementations on FPGAs using Intel’s oneAPI framework, addressing challenges in porting stencil-based computations from CPU/GPU architectures on FPGAs.FPGAs offer customizable hardware with on-chip memory that can be custom-tailored for High Performance Computing (HPC) applications.
Mordant, François-Xavier +3 more
openaire +2 more sources
A General and Efficient Framework for the Rapid Design of Miniaturized, Wideband, and High‐Bit RIS
A general and efficient framework is proposed for the rapid design of high‐performance reconfigurable intelligent surfaces (RISs). This framework integrates advanced antenna design techniques and incorporates various load types, quantities, and values to achieve the design of high‐performance RISs.
Jun Wei Zhang +14 more
wiley +1 more source
A New Method of Histogram Computation for Efficient Implementation of the HOG Algorithm
In this paper we introduce a new histogram computation method to be used within the histogram of oriented gradients (HOG) algorithm. The new method replaces the arctangent with the slope computation and the classical magnitude allocation based on ...
Mariana-Eugenia Ilas, Constantin Ilas
doaj +1 more source
Terahertz Channel Modeling, Estimation and Localization in RIS‐Assisted Systems
Reconfigurable intelligent surfaces have become a recent intensive research focus. Based on practical applications, channel strategies for RIS‐assisted terahertz wireless communication systems are categorized into three different types: channel modeling, channel estimation, and channel localization.
Hongjing Wang +9 more
wiley +1 more source
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley +1 more source

