Results 31 to 40 of about 20,255 (223)
Floating-Point Matrix Product on FPGA [PDF]
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Amira, A., Bensaali, F., Sotudeh, R.
core +2 more sources
An on‐demand ultra‐reconfigurable intelligent vision system with hierarchical reconfigurability from device to system levels is demonstrated. Through co‐design of a multi‐paradigm device, reconfigurable circuits, and adaptive system architecture/algorithms, the system enables seamless switching among spiking, non‐spiking, neuromorphic imaging (NI), and
Biyi Jiang +7 more
wiley +1 more source
Challenges in Clock Synchronization for On-Site Coding Digital Beamformer
Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors.
Satheesh Bojja Venkatakrishnan +2 more
doaj +1 more source
An Efficient Design of Anderson PUF by Utilization of the Xilinx Primitives in the SLICEM
Physical unclonable functions (PUFs) are known as one of the most recent promising technologies for cryptographic key generation. A PUF circuit is designed in such a way to produce random digits based on true-random and uncontrollable variations during ...
Armin Lotfy +3 more
doaj +1 more source
Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions [PDF]
In the past decade, Convolutional Neural Networks (CNNs) have demonstrated state-of-the-art performance in various Artificial Intelligence tasks. To accelerate the experimentation and development of CNNs, several software frameworks have been released ...
Bouganis, Christos-Savvas +2 more
core +2 more sources
A programmable 2048‐element circular ultrasound array combined with a compact acoustic lens produces a thin “sound sheet” over a large field of view, and records echoes with wide angular diversity across the ring aperture. Coherence‐enhanced beamforming converts full‐matrix data into high‐contrast tomographic slices, delivering near‐diffraction‐limited
Qiu‐De Zhang +11 more
wiley +1 more source
Proportional-Integral -Derivative Controller Using Embedded System Design Techniques
This paper aims to design a proportional-integral-derivative(PID)controller to be configured on field programmable gate arrays(FPGAs) using Embedded Design Techniques(EDTs).
Mazin R. Khalil, Saja B. Mahmood
doaj +1 more source
Testing for the programming circuit of LUT-based FPGAs [PDF]
The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs ...
Fujiwara, Hideo +4 more
core +1 more source
Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs) [PDF]
Abstract This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is ...
Segreen Ingersoll, Sotirios G. Ziavras
openaire +1 more source
Fabrication of High‐Density Multimodal Neural Probes Based on Heterogeneously Integrated CMOS
A chiplet‐based methodology democratizes active neural probe development on standard bulk CMOS services. This yields the first probe combining high‐density electrophysiology (416 electrodes) with calcium imaging (832 photodiodes) and complete on‐chip signal processing across 13 shanks.
Ju Hee Mun +10 more
wiley +1 more source

