Results 11 to 20 of about 1,658 (201)

Hardware acceleration of number theoretic transform for zk‐SNARK

Engineering Reports, EarlyView., 2023
An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao, Dong Ding, Feng Wang, Pengcheng Hua, Ning Wang, Qin Wu, Zhilei Chai   +6 more
wiley   +1 more source

XSBench on FPGAs using Intel oneAPI [PDF]

EPJ Web of Conferences
Field-Programmable Gate Arrays (FPGAs) are becoming an interesting component for heterogeneous computing systems in the post-Moore era thanks to their reconfigurable nature.
Pecák Oldřich, Matěj Zdeněk, Přenosil Václav   +2 more
doaj   +1 more source

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Applied Sciences, 2023
With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually ...
Weikun Xie, Wenjing Qi, Xiaohui Lin, Houjun Wang   +3 more
doaj   +1 more source

Image Processing Using FPGAs

Journal of Imaging, 2019
Nine articles have been published in this Special Issue on image processing using field programmable gate arrays (FPGAs). The papers address a diverse range of topics relating to the application of FPGA technology to accelerate image processing tasks ...
Donald G. Bailey
doaj   +1 more source

Hardware Realization of Generalized Time-Frequency Distribution with Complex-Lag Argument

EURASIP Journal on Advances in Signal Processing, 2009
A hardware implementation of the Nth order complex-lag time-frequency distribution is proposed. The considered distribution provides an arbitrary high concentration for multicomponent signals with fast varying instantaneous frequency.
Srdjan Stanković, Nikola Žarić, Irena Orović   +2 more
doaj   +1 more source

Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA Interconnects

IEEE Journal of the Electron Devices Society, 2015
We report a new nanoscale antifuse featuring low-power and high-programming speed, by employing silicon carbide (SiC) nanoelectromechanical systems (NEMS).
Tina He, Fengchao Zhang, Swarup Bhunia, Philip X.-L. Feng   +3 more
doaj   +1 more source

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

Sensors, 2014
The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption.
Gabriel J. García, Carlos A. Jara, Jorge Pomares, Aiman Alabdo, Lucas M. Poggi, Fernando Torres   +5 more
doaj   +1 more source

An On‐Demand Neuromorphic Vision System Enabled by a Multi‐Paradigm Neuromorphic Device and Hierarchical Reconfigurability Designed from Device to System Level

Advanced Science, EarlyView.
An on‐demand ultra‐reconfigurable intelligent vision system with hierarchical reconfigurability from device to system levels is demonstrated. Through co‐design of a multi‐paradigm device, reconfigurable circuits, and adaptive system architecture/algorithms, the system enables seamless switching among spiking, non‐spiking, neuromorphic imaging (NI), and
Biyi Jiang, Jiayi Xu, Liang Ran, Xinhe Feng, Khalil Harrabi, Yida Li, Longyang Lin, Feichi Zhou   +7 more
wiley   +1 more source

The NAIL Accelerator Interface Layer for Low Latency FPGA Offload

IEEE Access
We present the NAIL Accelerator Interface Layer, a framework for offloading accelerated computations to Field Programmable Gate Arrays served across the network.
Edward Grindley, Thurstan Gray, James Wilkinson, Chris Vaux, Adam Ardron, Jack Deeley, Alexander Elliott, Nidhin Thandassery Sumithran, Suhaib A. Fahmy   +8 more
doaj   +1 more source

Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

International Journal of Reconfigurable Computing, 2017
Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors.
Satheesh Bojja Venkatakrishnan, Elias A. Alwan, John L. Volakis   +2 more
doaj   +1 more source