Results 51 to 60 of about 7,998,069 (280)

Corrigendum

Advances in Mechanical Engineering, 2016
CORRIGENDUM A hybrid swarm intelligence of artificial immune system tuned with Taguchi–genetic algorithm and its field-programmable gate array realization to optimal inverse kinematics for an articulated industrial robotic manipulator Owing to errors ...
doaj   +1 more source

Simultaneous Enhancement of Performance and Stability in Dual‐Gate a‐IGZO Thin‐Film Transistors via Single‐Step Laser Annealing for Capacitor‐Less DRAM

Advanced Functional Materials, EarlyView.
A single‐step laser annealing strategy is presented for dual‐gate a‐IGZO TFTs. The steep thermal gradient induces graded oxygen doping in the channel and simultaneous WOx removal at the contacts, enabling concurrent interface and contact engineering.
Sihyeon Kwon, Junil Kim, Geuntae Park, Minseok Kim, Woohyun Hwang, Wanki Kim, Daewon Ha, Byeongmoon Lee, Jae Eun Jang, Hyuk‐Jun Kwon   +9 more
wiley   +1 more source

Ultrafast jet classification at the HL-LHC

Machine Learning: Science and Technology
Three machine learning models are used to perform jet origin classification. These models are optimized for deployment on a field-programmable gate array device.
Patrick Odagiu, Zhiqiang Que, Javier Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander Tapper, Thea K Årrestad   +15 more
doaj   +1 more source

Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

IEEE Access, 2019
Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of Field Programmable Gate Arrays (FPGA) highly ...
Prottay M. Adhikari, Hossein Hooshyar, Luigi Vanfretti   +2 more
doaj   +1 more source

Noise‐Limited Bit Precision in Ferroelectric Synaptic Transistors for High‐Resolution Neuromorphic Computing

Advanced Functional Materials, EarlyView.
Low‐frequency noise spectroscopy defines the resolvable conductance states of synaptic FeFETs by coupling read‐current fluctuation with usable dynamic range. The resulting noise‐limited bit precision establishes a universal, device‐agnostic reliability metric beyond the memory window, enabling quantitative benchmarking and rational design of high ...
Jaehong Park, Yeonseop Shin, Changhyeon Han, Sangwoo Kim, Eunchan Park, Youngchan Cho, Jaehong Min, Hyunjun Ahn, Jaekyoung Park, Cheol‐Woong Yang, Jangsaeng Kim, Daewoong Kwon, Wonjun Shin   +12 more
wiley   +1 more source

Implementation of Reed-Solomon Encoder/Decoder Using Field Programmable Gate Array

Journal of Engineering and Sustainable Development, 2006
In this paper, (15, 11) and (255, 239) Reed-Solomon codes have been designed and Implemented using ALTERA Field Programmable Gate Array (FPGA) device. The design is carried out by writing VHDL modules for different encoder and decoder components.
Hikmat N. Abdullah
doaj  

Light‐Induced Field‐Tunneling Synapses in Solution‐Processed Van Der Waals Heterostructures for Scalable, Retina‐Inspired Optical Sensing

Advanced Functional Materials, EarlyView.
A scalable, solution‐processed WSe2/ZrO2‐x van der Waals heterostructure realizes a light‐induced field‐tunneling synapse (LIFTS) that activates exclusively under bright illumination, emulating the photopic adaptation of the human retina at the device level.
Kijeong Nam, Jihyun Kim, Soobeen Ji, In Soo Kim, Sejin Kim, Eungseon Yeon, Do Kyung Hwang, Iva Plutnarová, Zdeněk Sofer, Sang Min Won, Joohoon Kang   +10 more
wiley   +1 more source

Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing

Advanced Functional Materials, EarlyView.
A Memristive‐Gated Transistor for Time‐Encoded Analog In‐Memory Computing — By exploiting the RC delay of a self‐rectifying interface‐type memristor, nonlinear I–V distortion is structurally bypassed, enabling 3‐bit nonvolatile memory, spike‐timing‐based analog encoding, and hardware‐calibrated reservoir‐computing validation within a unified device ...
Yun‐Seo Shin, Eunjoo Yoo, Ki‐Hoon Son, Hyun‐Sik Kim, Dae‐Hee Han, Jeong Hyeon Son, Seung Hwan Lee, Hong‐Sub Lee   +7 more
wiley   +1 more source

Emerging Post‐CMOS Hardware Neurons for Brain‐Inspired Computing: Devices, Circuits, and System Integration

Advanced Functional Materials, EarlyView.
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan, Hocheon Yoo, Benoît H. Lessard, Ioannis Kymissis, Chang‐Hyun Kim   +4 more
wiley   +1 more source

An efficient AES implementation using FPGA with enhanced security features

Journal of King Saud University: Engineering Sciences, 2020
Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security ...
Harshali Zodpe, Ashok Sapkal
doaj   +1 more source