Results 51 to 60 of about 91,286 (241)
PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]
, 2007 We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki +2 more
core +2 more sources
Implementación del algoritmo Threefish-256 en hardware reconfigurable
Iteckne, 2014 This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process.
Nathaly Nieto-Ramírez +1 more
doaj +1 more source
An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes
, 2017 Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds ...
Chen, Ji +6 more
core +1 more source
The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design
ComputersThe emergent field of embedded computing presents a challenging scenario for ubiquitous music (ubimus) design. Available tools demand specific technical knowledge—as exemplified in the techniques involved in programming integrated circuits of ...
Damián Keller +2 more
doaj +1 more source
Realization of Three-level SVPWM Algorithm Based on FPGA
机车电传动, 2016 According to the performance of AC-driving digital control system greatly depends on the process speed of controller, field programmable gate array(FPGA) was introduced to reduce the control period. Three-levels space vector pulse width modulation(SVPWM)
LIN Xin, KOU Shuren, YANG Fan
doaj
IEEE AccessAdvanced memory optimization techniques are reviewed to enhance the performance of Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs) on hardware accelerators, addressing the real-world challenges in medical imaging.
N. Srikanth Prasad, S. Sundar
doaj +1 more source
Implementation of Edge Detection Digital Image Algorithm on a FPGA
MATEC Web of Conferences, 2016 This paper presents the implementation of an adaptive contour detection filter on field programmable gate array (FPGA) using a combination of hardware and software components.
Bouganssa Issam +2 more
doaj +1 more source
FPGA as a tool for hardware realization of feedback control
Journal of Electrical Systems and Information Technology, 2015 The presented paper deals with the development of robust control algorithm based on reflection vectors methodology. This approach of controller design is guaranteeing stability, robustness and high performance.
Ján Cigánek +2 more
doaj +1 more source
Implementasi Field Programmable Gate Array Dalam Perancangan Arithmetic-Logic Unit Dan Shifter [PDF]
, 2013 Paper ini membahas mengenai implementasi Field Programmable Gate Array (FPGA) untuk membuat Arithmetic-Logic Unit (ALU) merupakan core dari central processing unit (CPU). ALU terdiri dari dua fungsi, yaitu unit aritmetik dan unit logik.
Wibowo, F. W. (Ferry)
core
International Journal of Reconfigurable Computing, 2022 In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board.
Peter Jamieson +4 more
doaj +1 more source