Results 51 to 60 of about 46,893 (234)

A General and Efficient Framework for the Rapid Design of Miniaturized, Wideband, and High‐Bit RIS

Advanced Electronic Materials, EarlyView.
A general and efficient framework is proposed for the rapid design of high‐performance reconfigurable intelligent surfaces (RISs). This framework integrates advanced antenna design techniques and incorporates various load types, quantities, and values to achieve the design of high‐performance RISs.
Jun Wei Zhang, Zheng Xing Wang, Wanwan Cao, Zhen Jie Qi, Li Jie Wu, Han Qing Yang, Qun Yan Zhou, Si Ran Wang, Hui Dong Li, Jun Yan Dai, Jiang Luo, Jun Wei Wu, Jia Nan Zhang, Zhen Zhang, Qiang Cheng   +14 more
wiley   +1 more source

Implementación del algoritmo Threefish-256 en hardware reconfigurable

Iteckne, 2014
This article  presents  both  the  description and  results  of  the Threefish  cryptographic  algorithm hardware  implementation  for  encryption  process.
Nathaly Nieto-Ramírez, Rubén Darío Nieto-Londoño   +1 more
doaj   +1 more source

A Polymorphic Reconfigurable Multi‐Electrode Device Based on Electrically Bistable Nanostructured Metallic Films

Advanced Electronic Materials, EarlyView.
A polymorphic reconfigurable multi‐electrode device based on electrically bistable nanostructured metallic films. The adaptive reconfiguration properties of the nanostructured network under specific input voltages drive the reprogrammability of the device. This system can be employed for the implementation of polymorphic devices, which can be used both
Silvia Bressan, Luca Camillini, Francesca Borghi, Giovanni Galafassi, Paolo Milani   +4 more
wiley   +1 more source

The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design

Computers
The emergent field of embedded computing presents a challenging scenario for ubiquitous music (ubimus) design. Available tools demand specific technical knowledge—as exemplified in the techniques involved in programming integrated circuits of ...
Damián Keller, Aman Jagwani, Victor Lazzarini   +2 more
doaj   +1 more source

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series [PDF]

, 2002
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically ...
David Robinson, Eh Bh, Ian Robertson, James Irvine, Patrick Lysaght   +4 more
core   +2 more sources

Cryogenic Neuromorphic Synaptic Behavior in 180 nm Silicon Transistors for Emerging Computing Systems

Advanced Intelligent Systems, EarlyView.
This study investigates the neuromorphic plasticity behavior of 180 nm bulk complementary metal oxide semiconductor (CMOS) transistors at cryogenic temperatures. The observed hysteresis data reveal a signature of synaptic behavior in CMOS transistors at 4 K.
Fiheon Imroze, Bhavani Yalagala, Naveen Kumar, Mostafa Elsayed, Meraj Ahmad, Robert Graham, Vihar Georgiev, Hadi Heidari, Martin Weides   +8 more
wiley   +1 more source

Implementasi Field Programmable Gate Array Dalam Perancangan Arithmetic-Logic Unit Dan Shifter [PDF]

, 2013
Paper ini membahas mengenai implementasi Field Programmable Gate Array (FPGA) untuk membuat Arithmetic-Logic Unit (ALU) merupakan core dari central processing unit (CPU). ALU terdiri dari dua fungsi, yaitu unit aritmetik dan unit logik.
Wibowo, F. W. (Ferry)
core  

PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]

, 2007
We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki, Hamada, Tsuyoshi, Makino, Junichiro   +2 more
core   +2 more sources

Securing Generative Artificial Intelligence with Parallel Magnetic Tunnel Junction True Randomness

Advanced Intelligent Systems, EarlyView.
True random numbers can protect generative artificial intelligence (GAI) models from attacks. A highly parallel, spin‐transfer torque magnetic tunnel junction‐based system is demonstrated that generates high‐quality, energy‐efficient random numbers.
Youwei Bao, Shuhan Yang, Hyunsoo Yang
wiley   +1 more source

Realization of Three-level SVPWM Algorithm Based on FPGA

机车电传动, 2016
According to the performance of AC-driving digital control system greatly depends on the process speed of controller, field programmable gate array(FPGA) was introduced to reduce the control period. Three-levels space vector pulse width modulation(SVPWM)
LIN Xin, KOU Shuren, YANG Fan
doaj