Interconnect Solutions for Virtualized Field-Programmable Gate Arrays
IEEE Access, 2018 Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA).
Sadegh Yazdanshenas, Vaughn Betz
doaj +2 more sources
Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays
IEEE Access, 2018 The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect.
Tian Qin +4 more
doaj +2 more sources
Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review [PDF]
SensorsA fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization.
Diego Real, David Calvo
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A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs) [PDF]
Sensors, 2013 This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability ...
Carlos Gómez Osuna +2 more
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Sequential Discrete Kalman Filter for Real-Time State Estimation in Power Distribution Systems: Theory and Implementation [PDF]
IEEE Transactions on Instrumentation and Measurement, Volume 66,
Issue 9, September 2017, 2017 This paper demonstrates the feasibility of implementing Real-Time State Estimators (RTSEs) for Active Distribution Networks (ADNs) in Field-Programmable Gate Arrays (FPGAs) by presenting an operational prototype.
Kettner, Andreas Martin, Paolone, Mario
core +2 more sources
A Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Arrays [PDF]
, 2007 An artificial neural network algorithm is implemented using a field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time ...
Badala +10 more
core +3 more sources
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays
Journal of Information Processing, 2014 : In this study, the properties of physical unclonable functions (PUFs) for 28-nm process field-programmable gate arrays (FPGAs) are examined. A PUF is a circuit that generates device-specific IDs by extracting device variations. Owing to device variation,
Y. Hori +5 more
semanticscholar +2 more sources
Optical Multi-Context Blind Scrubbing for Field Programmable Gate Arrays
IEEE Photonics Journal, 2020 This paper presents a proposal of a new optical multi-context blind scrubbing that can not only increase the soft-error tolerance of the configuration memory of field programmable gate arrays (FPGAs) but also support high-speed dynamic reconfiguration ...
Yusuke Takaki, Minoru Watanabe
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Autoencoders on field-programmable gate arrays for real-time, unsupervised new physics detection at 40 MHz at the Large Hadron Collider [PDF]
Nature Machine Intelligence, 2021 To study the physics of fundamental particles and their interactions, the Large Hadron Collider was constructed at CERN, where protons collide to create new particles measured by detectors.
E. Govorkova +13 more
semanticscholar +1 more source
FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers
IEEE Access, 2023 The Karatsuba algorithm is an effective way to accelerate large integer multiplications through recursive function calls. However, existing hardware implementations of Karatsuba multipliers are limited to fixed operand sizes.
Byeongmin Kang, Hyungmin Cho
doaj +1 more source