Comparison of bulk FinFET and SOI FinFET [PDF]
MATEC Web of Conferences, 2018 In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software.
Chen Ying-Yu, Lin Yu-Hsien
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Silicon-on-Insulator (SOI) Lateral Power-Reduced Surface Field FinFET with High-Power Figure of Merit of 239.3 MW/cm2 [PDF]
MicromachinesIn this study, we propose a lateral power-reduced surface field FinFET (LPR-FinFET) to achieve high breakdown voltage and low on-resistance. We investigate the electric field distribution within the reduced surface field (RESURF) structure under reverse ...
Chang Woo Song +4 more
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Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET [PDF]
Nanomaterials, 2023 FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe ...
Shixin Li, Zhenhua Wu
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High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET [PDF]
Nanomaterials, 2023 This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy.
Yi-Ju Yao +8 more
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High performance and low leakage heterojunction 10 nm PZT NC-FinFET for low power application [PDF]
Scientific ReportsIncreasing transistor integration density and increased power are the significant challenges for designers at lower transistor technology nodes. However, scaling down the transistor leads to the uneven change in threshold voltage with scaled supply ...
Suman Lata Tripathi +3 more
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Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset [PDF]
MicromachinesPlanar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses
Hongwei Zhang +6 more
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A Stepped-Spacer FinFET Design for Enhanced Device Performance in FPGA Applications [PDF]
MicromachinesAs transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability.
Meysam Zareiee +2 more
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Dopant metrology in advanced FinFETs [PDF]
, 2011 Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. This paper describes how, through correlation of experimental data with multimillion atom tight-binding simulations using ...
Hollenberg, L. C. L. +6 more
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Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET
IEEE Access, 2023 Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting gate-all-around (GAA) device architecture. However, compared against FinFET device structure, the GAA device is not very cost-effective.
Myoungsu Son +3 more
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Micromachines, 2022 In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE).
Changwoo Noh +3 more
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