Results 101 to 110 of about 11,359 (209)

Design of a Low-Area, Low-Power and High-Speed Comparator in 65 nm FinFET Technology

open access: yesمهندسی مخابرات جنوب
In the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and ...
Navid Sabzevari   +2 more
doaj  

Benchmarking the screen-grid field effect transistor (SGrFET) for digital applications

open access: yes, 2010
Continuous scaling of CMOS technology has now reached a state of evolution, therefore, novel device structures and new materials have been proposed for this purpose.
Shadrokh, Yasaman, Shadrokh, Yasaman
core   +1 more source

Depletion-Isolation Effect in Vertical MOSFETs During the Transition From Partial to Fully Depleted Operation

open access: yes, 2006
A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm.
Ashburn, Peter   +5 more
core   +1 more source

Design of 30 nm negative capacitance FinFET using PZT for high-speed processors

open access: yesDiscover Materials
FinFETs are promising candidates for reduced transistor dimensions, showing a high switching current ratio and better subthreshold performance. It shows better gate control over the channel due to multiple gates, including side and top gates.
Suman Lata Tripathi   +2 more
doaj   +1 more source

Low power area efficient self-gated flip flop: Design, implementation and analysis in emerging devices

open access: yesEngineering and Applied Science Research, 2022
This study presents a novel CMOS self-gated flip flop for low power and area efficient applications. The low power operations are achieved by deactivating the clock signal when not required in the circuit.
Owais Ahmad Shah   +2 more
doaj  

Enhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs

open access: yes, 2016
FinFET technology is prone to suffer from Line Edge Roughness (LER) based VT variation with scaling. To address this, we proposed an Epitaxially Defined (ED) FinFET (EDFinFET) as an alternate to FinFET architecture for 10 nm node and beyond. We showed by statistical simulations that EDFinFET reduces LER based VT variability by 90% and overall ...
Mittal, Sushant   +4 more
openaire   +2 more sources

Transistores FinFET

open access: yes, 2010
[spa] El presente articulo pretende dar a conocer los dispositivos FinFET, que ventajas presenta su estructura frente a los dispositivos MOS clásicos, cual es el estado del arte actual y finalmente, cual es el impacto de este tipo de transistor en el mercado.
Mas Boned, Francisco de Borja   +1 more
openaire   +1 more source

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

open access: yes, 2019
Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip
Bol, David   +2 more
core   +1 more source

AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications

open access: yesIEEE Journal of the Electron Devices Society
Fin Field-Effect-Transistor (FinFET) has become fundamental components in advanced integrated circuit, while the drain-extended FinFET (DE-FinFET) features a lightly doped drain extension region to improve the device’s breakdown voltage.
Xiaoyun Huang   +7 more
doaj   +1 more source

Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation

open access: yes, 2006
A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm.
Ashburn, P.   +5 more
core  

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