Results 91 to 100 of about 7,054 (167)
A series of zinc(II) porphyrin‐based D−A complexes is employed to fabricate solution‐processable resistive memory devices. The utilization of an electron‐donating π‐bridge or a weak electron‐donating moiety is able to turn on an extra resistive state to realize ternary memory performance, demonstrating the relationship between memory behavior and ...
Ka Wai Kwong +5 more
wiley +1 more source
Enhancement‐mode monolayer MoS2 FETs with low threshold voltage are essential for low‐power electronics. The threshold voltage can be tuned by the gate metal work function when the semiconductor/dielectric interface is clean. Interfaces between monolayer MoS2 and ZrO2 or hBN allow effective work‐function modulation of the threshold voltage, in contrast
Lixin Liu +10 more
wiley +1 more source
A Model of Threshold Voltage in FinFET
A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation.
X.H. Zhang, Jian Liu, Li Li
core +1 more source
PERFORMANCE COMPARISON OF BULK FINFET WITH SOI FINFET IN NANO-SCALE REGIME [PDF]
This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper
TRIPATHI, SUMANLATA +5 more
core +1 more source
Comparative Study on RTN Amplitude in Planar and FinFET Devices
In this paper, the amplitude of random telegraph noise (RTN) in FinFET is studied, comparing with RTN in planar devices. The impacts of intrinsic characteristics in FinFET (channel non-uniformity and quantum confinement) on its RTN amplitude are ...
Asenov, Asen +15 more
core +1 more source
Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits
As technological nodes are scaled down to the nanoscale, power consumption emerges as a critical challenge in complementary metal‐oxide‐semiconductor (CMOS) technology.
Pillem Ramesh, Atul S. M. Tripathi
doaj +1 more source
This study presents a novel CMOS self-gated flip flop for low power and area efficient applications. The low power operations are achieved by deactivating the clock signal when not required in the circuit.
Owais Ahmad Shah +2 more
doaj
A New Extended Body FinFET for 1T-DRAM Application
In this paper, we propose a new extended body FinFET (EB-FinFET) for one transistor dynamic random access memory (1T-DRAM) application. As the device scales down, 1T-DRAM faces the challenge of an insufficient storage region.
Chang, Cheng-Hsien
core
Performance and Leakage Optimization with 22nm Bi-level FinFET
In this paper, we analyze on- and off-current characteristic of the 22-nm Bi-level FinFET in which two different fin widths are formed. From the 3D Technology CAD (TCAD) simulations, we find out that the narrower the fin width the lower the leakage ...
Jaemin Lee +3 more
core +1 more source
Design of a Low-Area, Low-Power and High-Speed Comparator in 65 nm FinFET Technology
In the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and ...
Navid Sabzevari +2 more
doaj

