A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology [PDF]
, 2009 The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a ...
Annema, A.J. +3 more
core +2 more sources
Statistical variability and reliability in nanoscale FinFETs [PDF]
, 2011 A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented.
Asenov, A. +3 more
core +1 more source
Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance [PDF]
, 2014 In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors.
Amoroso, Salvatore Maria +7 more
core +1 more source
Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications [PDF]
, 2017 In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology.
Adamu-Lema, F. +3 more
core +1 more source
A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology [PDF]
, 2016 A simple device-level characterization approach to quantitatively evaluate the impacts of different random variation sources in FinFETs is proposed. The impacts of random dopant fluctuation are negligible for FinFETs with lightly doped channel, leaving ...
Asenov, Asen +6 more
core +2 more sources
Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs [PDF]
, 2017 The characteristic performance of n-type and p-type inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode, bulk Germanium FinFET device with 3-nm gate length (LG) are demonstrated by using 3-D quantum transport device simulation.
Asenov, Asen +11 more
core +1 more source
Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics
Nanomaterials, 2021 In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented.
Yongliang Li +9 more
doaj +1 more source
Performance evaluation of SRAM design using different field effect transistors [PDF]
E3S Web of Conferences, 2023 SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it.
C. Venkataiah +5 more
doaj +1 more source
HAADF-STEM block-scanning strategy for local measurement of strain at the nanoscale
, 2020 Lattice strain measurement of nanoscale semiconductor devices is crucial for the semiconductor industry as strain substantially improves the electrical performance of transistors.
Bender, Hugo +5 more
core +2 more sources
Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide
Memories - Materials, Devices, Circuits and Systems, 2023 This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence
Vandana Singh Rajawat +2 more
doaj +1 more source