Results 41 to 50 of about 11,328 (210)

Improved effective mobility extraction in MOSFETs [PDF]

, 2009
The standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed.
Baccarani, Chen, Chow, D.R. Leadley, E.H.C. Parker, G. Vellianitis, Huang, J.R. Watling, Jungemann, Kilchytska, Koga, Koomen, R.J.P. Lander, Ramos, S.M. Thomas, Schmitz, Schroder, Sodini, T.E. Whall, Takagi, Vasileska, Wang, Zebrev, Zeitzoff   +23 more
core   +1 more source

Harnessing Time‐Dependent Magnetic Texture Dynamics via Spin‐Orbit Torque for Physics‐Enhanced Neuromorphic Computing

Advanced Science, EarlyView.
A neuromorphic computing platform using spin‐orbit torque‐controlled magnetic textures is reported. The device implements bio‐inspired synaptic functions and achieves high performance in both pattern recognition (>93%) and combinatorial optimization (>95%), enabling unified processing of cognitive and optimization tasks.
Yifan Zhang, Yu Li, Huai Lin, Xinying Wang, Long Liu, Guoliang Xing, Di Wang, Zhihao Zhao, Zhipeng Guo, Junbo Yang, Jiebin Niu, Yan Sun, Tom Wu, Guozhong Xing   +13 more
wiley   +1 more source

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

Memories - Materials, Devices, Circuits and Systems
In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length.
Priyanka Agrwal, Ajay Kumar
doaj   +1 more source

Engineered Strain in 2D Materials by Direct Growth on Deterministically Patterned Grayscale Topographies

Advanced Science, EarlyView.
ABSTRACT Strain is a proven technique for modifying the bandgap and enhancing carrier mobility in 2D materials. Most current strain engineering techniques rely on the post‐growth transfer of these atomically thin materials from growth substrates to target surfaces, limiting their integration into nanoelectronics.
Berke Erbas, Arindam Bala, Hernan Furci, Anushree Dutta, Naresh Kumar, Renato Zenobi, Giovanni Boero, Andras Kis, Juergen Brugger   +8 more
wiley   +1 more source

Review of Nanosheet Transistors Technology

Tikrit Journal of Engineering Sciences, 2021
Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET ...
Firas .. Agha, Yasir .. Naif, Mohammed .. Shakib   +2 more
doaj   +1 more source

Modelling and simulation of advanced semiconductor devices [PDF]

, 2017
This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here.
Adamu-Lema, Fikru, Al-Ameri, T., Asenov, Asen, Berrada, Salim, Duan, Meng, Georgiev, Vihar, Lee, Jaehyun   +6 more
core   +1 more source

Machine Learning‐Based Standard Compact Model Binning Parameter Extraction Methodology for Integrated Circuit Design of Next‐Generation Semiconductor Devices

Advanced Intelligent Systems, EarlyView.
This study presents a neural network‐based methodology for Berkeley Short‐Channel IGFET Model–Common Multi‐Gate parameter extraction of gate‐all‐around field effect transistors, integrating binning adaptive sampling and transformer neural networks to efficiently capture current–voltage and capacitance–voltage characteristics.
Jaeweon Kang, Johyeon Kim, Sueyeon Kim, Hyunbo Cho, Jongwook Jeon   +4 more
wiley   +1 more source

Improvement of the Drive Current in 5nm Bulk-FinFET Using Process and Device Simulations [PDF]

Journal of Optoelectronical Nanostructures, 2020
: We present the optimization of the manufacturing process of the 5nm bulk-FinFET technology by using the 3D process and device simulations. In this paper, bysimulating the manufacturing processes, we focus on optimizing the manufacturingprocess to ...
Payman Bahrami, Mohammad Reza Shayesteh, Majid Pourahmadi, Hadi Safdarkhani   +3 more
doaj  

Correlation between the golden ratio and nanowire transistor performance [PDF]

, 2018
An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi).
Al-Ameri, Talib
core   +1 more source

Fully CMOS‐Compatible 3‐T Embedded NOR Flash Memory Achieving 28 ns Long‐Term Potentiation/Long‐Term Depression for High‐Speed Online Training Accelerators

Advanced Intelligent Systems, EarlyView.
A fully complementary metal–oxide–semiconductor process‐compatible novel 3‐T embedded NOR flash is demonstrated on a 28 nm fully depleted silicon‐on‐insulator platform. The proposed memory achieves record‐fast 28‐long‐term potentiation and depression , offering high‐speed and highly reliable synaptic behavior for online training in neuromorphic ...
Jae Seung Woo, Kyoung Min Choi, Geun Tae Park, Jin Ho Chang, Woo Young Choi   +4 more
wiley   +1 more source