Results 71 to 80 of about 11,359 (209)

Ultrathin Hafnium‐Based Ferroelectric Devices for In‐Memory Computing Applications

Information &Functional Materials, Volume 3, Issue 1, Page 8-34, March 2026.
Hafnium‐based ferroelectric devices exhibit advantages in nonvolatile storage, low power consumption, and ultrahigh operation speed, positioning them as strong candidates for constructing hardware neural networks. ABSTRACT The discovery of ferroelectricity in HfO2‐based ferroelectrics at the ultrathin scale has reignited enthusiasm for ferroelectric ...
Chenghong Mo, Zheng Wang, Jialin Meng, Tianyu Wang   +3 more
wiley   +1 more source

Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

, 2010
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior.
Biesemans, Serge, Collaert, Nadine, Klimeck, Gerhard, Lee, Sunhee, Mehrotra, Saumitra R., Paul, Abhijeet, Rogge, Sven, Tettamanzi, Giuseppe Carlo   +7 more
core   +1 more source

Harnessing Time‐Dependent Magnetic Texture Dynamics via Spin‐Orbit Torque for Physics‐Enhanced Neuromorphic Computing

Advanced Science, Volume 13, Issue 12, 27 February 2026.
A neuromorphic computing platform using spin‐orbit torque‐controlled magnetic textures is reported. The device implements bio‐inspired synaptic functions and achieves high performance in both pattern recognition (>93%) and combinatorial optimization (>95%), enabling unified processing of cognitive and optimization tasks.
Yifan Zhang, Yu Li, Huai Lin, Xinying Wang, Long Liu, Guoliang Xing, Di Wang, Zhihao Zhao, Zhipeng Guo, Junbo Yang, Jiebin Niu, Yan Sun, Tom Wu, Guozhong Xing   +13 more
wiley   +1 more source

Engineered valley-orbit splittings in quantum confined nanostructures in silicon [PDF]

, 2011
An important challenge in silicon quantum electronics in the few electron regime is the potentially small energy gap between the ground and excited orbital states in 3D quantum confined nanostructures due to the multiple valley degeneracies of the ...
G. Klimeck, G. Klimeck, G. P. Lansbergen, J. Verduijn, L. C. L. Hollenberg, N. Kharche, R. Rahman, S. Rogge   +7 more
core   +4 more sources

Machine Learning‐Based Standard Compact Model Binning Parameter Extraction Methodology for Integrated Circuit Design of Next‐Generation Semiconductor Devices

Advanced Intelligent Systems, Volume 8, Issue 2, February 2026.
This study presents a neural network‐based methodology for Berkeley Short‐Channel IGFET Model–Common Multi‐Gate parameter extraction of gate‐all‐around field effect transistors, integrating binning adaptive sampling and transformer neural networks to efficiently capture current–voltage and capacitance–voltage characteristics.
Jaeweon Kang, Johyeon Kim, Sueyeon Kim, Hyunbo Cho, Jongwook Jeon   +4 more
wiley   +1 more source

FinFET to GAA MBCFET: A Review and Insights

IEEE Access
This review article presents a journey from Fin-shaped field effect transistor (FinFET) to gate-all-around multi-bridge channel field effect transistor (GAA MBCFET) technology, unraveling the evolution of semiconductor architectures.
Rinku Rani Das, T. R. Rajalekshmi, Alex James   +2 more
doaj   +1 more source

HFinFET: A Scalable, High Performance, Low Leakage Hybrid N-Channel FET

, 2010
In this letter we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of a HEMT and a FinFET, to obtain excellent performance and good off state control.
Bhat, Navakanta, Jammy, Raj, Majhi, Prashant, Majumdar, Kausik   +3 more
core   +1 more source

Multi-cell soft errors at the 16-nm FinFET technology node [PDF]

, 2015
Soft error performance of 16-nm FinFET SRAM designs fabricated using a commercial bulk CMOS process is evaluated using heavy-ions. Results included supply voltage variations show that multi-cell upsets dominate soft-error rates. Dual-port SRAM has higher
Alles, M. L., Ball, D., Bhuva, B. L., Chatterjee, I., Massengill, L. W., McCurdy, M., Tam, N.   +6 more
core   +2 more sources

Fully CMOS‐Compatible 3‐T Embedded NOR Flash Memory Achieving 28 ns Long‐Term Potentiation/Long‐Term Depression for High‐Speed Online Training Accelerators

Advanced Intelligent Systems, Volume 8, Issue 2, February 2026.
A fully complementary metal–oxide–semiconductor process‐compatible novel 3‐T embedded NOR flash is demonstrated on a 28 nm fully depleted silicon‐on‐insulator platform. The proposed memory achieves record‐fast 28‐long‐term potentiation and depression , offering high‐speed and highly reliable synaptic behavior for online training in neuromorphic ...
Jae Seung Woo, Kyoung Min Choi, Geun Tae Park, Jin Ho Chang, Woo Young Choi   +4 more
wiley   +1 more source

Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs [PDF]

, 2016
The fin-edge roughness (FER) and the TiN metal grain work function (MGW)-induced variability affecting OFF and ON device characteristics are studied and compared between a 10.4 nm gate length In0.53Ga0.47As FinFET and a 10.7 nm gate length Si FinFET.
Aldegunde, Manuel, Elmessary, Muhammad A., Garcia-Loureiro, Antonio J., Indalecio, G., Kalna, Karol, Nagy, Daniel, Seoane, N.   +6 more
core   +1 more source