Results 81 to 90 of about 11,328 (210)
FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability [PDF]
, 2018 Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools.
Elmessary, Muhammad A. +4 more
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Advanced Materials, Volume 37, Issue 50, December 17, 2025.HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zuopu Zhou +9 more
wiley +1 more source
Sensors, 2020 Wireless Capsule Endoscopy is a state-of-the-art technology for medical diagnoses of gastrointestinal diseases. The amount of data produced by an endoscopic capsule camera is huge.
Ioannis Intzes +2 more
doaj +1 more source
Simulating Scaling Effects in Fully Vertical GaN FinFETs
physica status solidi (a), Volume 222, Issue 23, December 2025.Vertical GaN‐on‐GaN unipolar FinFETs have been analyzed and optimized using TCAD modeling. Simulations varying the device dimensions—fin width, height, spacing, and drift layer thickness—have been done. Device designs which optimize the Baliga's figure of merit, breakdown voltage, and switching losses are presented.
Alexander Simko +4 more
wiley +1 more source
Multi-Channel Step FinFET With Spacer Engineering
IEEE AccessMulti-channel FinFET ( $\text{M}_{\textbf {ch}}$ -FinFET) is an emerging device having promising use due to its excellent driving capability. In this paper, we have investigated the significance of multiple channels of FinFET configuration.
Rinku Rani Das, Alex James
doaj +1 more source
BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits
Active and Passive Electronic Components, 2019 This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits.
Haiyan Ni +3 more
doaj +1 more source
Small Science, Volume 5, Issue 12, December 2025.This article reports a multiscale investigation of monolayer MoS2 field‐effect transistors, revealing a source/drain Schottky barrier of ≈0.21 eV and contact‐induced strain variations inside the channel. The impact of strain inhomogeneities on the electron effective mass (meff) distribution and their implications on carrier mobility and contact ...
Salvatore Ethan Panasci +17 more
wiley +1 more source
IET Circuits, Devices and SystemsThe geometrical parameters of the fin-shaped field-effect transistor (FinFET) significantly affect the outcomes of the FinFET-based designs. Various machine learning (ML) schemes have been presented to optimize the geometrical parameters of the FinFET ...
Vijayalaxmi Kumbar, Manisha Waje
doaj +1 more source
Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor
IEEE Journal of the Electron Devices Society, 2017 The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the ...
Eunah Ko +4 more
doaj +1 more source
Multi-port Memory Design for Advanced Computer Architectures [PDF]
, 2013 In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters.
Zhao, Yirong
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