Results 31 to 40 of about 36,845 (298)

Architecture and Process Integration Overview of 3D NAND Flash Technologies

Applied Sciences, 2021
In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties.
Geun Ho Lee, Sungmin Hwang, Junsu Yu, Hyungjin Kim   +3 more
doaj   +1 more source

EDACs and test integration strategies for NAND flash memories [PDF]

, 2010
Mission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device
Piazza, R., Stefano Di Carlo, Michele Fabiano, Politecnico Di Torino, Fabiano, Michele, Paolo Prinetto, Prinetto, Paolo Ernesto, Roberto Piazza, Piazza R., Di Carlo, Stefano   +9 more
core   +1 more source

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories [PDF]

, 2012
In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage ...
C. Zambelli, P. Olivo, Indaco, Marco, Olivo P., M. Indaco, BERTOZZI, Davide, Zambelli, C., Di Carlo, Stefano, Olivo, P., Bertozzi D., P. Prinetto, D. Bertozzi, M. Fabiano, ZAMBELLI, Cristian, OLIVO, Piero, Fabiano, Michele, Prinetto, Paolo Ernesto, S. Di Carlo, Bertozzi, D., Zambelli C.   +19 more
core   +1 more source

Research and Design of Nand Flash Array From Host to Flash Translation Layer

IEEE Access, 2023
Given the inherent limitations of flash memory, solid-state storage devices require a host controller and a flash translation layer (FTL) to address two major conflicts: the conflict between the limited erase endurance of flash memory and the expectation
Boyang Ding, Songyan Liu, Tao Lv, Yao Liu, Wenbin Lu   +4 more
doaj   +1 more source

A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories

Micromachines, 2021
Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology.
Michele Favalli, Cristian Zambelli, Alessia Marelli, Rino Micheloni, Piero Olivo   +4 more
doaj   +1 more source

Flash drought fades away under the effect of accumulated water deficits: the persistence and transition to conventional drought

Environmental Research Letters, 2023
Flash drought typically refers to the rapid intensification process that would only persist for a certain amount of time. In spite of short duration, flash drought may cause destructive impacts on agricultural and ecological sectors due to the sustained ...
Yi Liu, Ye Zhu, Liliang Ren, Vijay P Singh, Shanshui Yuan   +4 more
doaj   +1 more source

On coding efficiency for flash memories [PDF]

2012 35th IEEE Sarnoff Symposium, 2012
Recently, flash memories have become a competitive solution for mass storage. The flash memories have rather different properties compared with the rotary hard drives. That is, the writing of flash memories is constrained, and flash memories can endure only limited numbers of erases.
openaire   +2 more sources

Protograph QC-LDPC and Rate-Adaptive Polar Codes Design for MLC NAND Flash Memories

IEEE Access, 2019
A protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) code for multi-level cell (MLC) NAND flash memories is proposed in this paper. In this design approach, the quantized voltage signals are measured for soft decoding because the exact ...
Lingjun Kong, Yahui Liu, Haiyang Liu, Shengmei Zhao   +3 more
doaj   +1 more source

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines, 2021
Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories.
Fei Chen, Bo Chen, Hongzhe Lin, Yachen Kong, Xin Liu, Xuepeng Zhan, Jiezhi Chen   +6 more
doaj   +1 more source

MEDEA: A Hybrid Shared-memory/Message-passing Multiprocessor NoC-based Architecture [PDF]

, 2010
The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose chip multiprocessors (CMPs) to domain specific multi-core ...
Ruo Roch, Massimo, Luca Rostagno, Rostagno, Luca, Casu, Mario Roberto, Sergio V Tota, TOTA, Sergio Vincenzo, Tota S.V, Zamboni, Maurizio, Mario R Casu, Massimo Ruo Roch, Maurizio Zamboni   +10 more
core   +1 more source