Results 71 to 80 of about 384,291 (294)
FPGA-Based Bandwidth Selection for Kernel Density Estimation Using High Level Synthesis Approach
, 2015 FPGA technology can offer significantly hi\-gher performance at much lower power consumption than is available from CPUs and GPUs in many computational problems.
Gramacki, Artur +2 more
core +1 more source
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations [PDF]
Symposium on Field Programmable Gate Arrays, 2020 Binary neural networks (BNNs) have 1-bit weights and activations. Such networks are well suited for FPGAs, as their dominant computations are bitwise arithmetic and the memory requirement is also significantly reduced.
Yichi Zhang +5 more
semanticscholar +1 more source
Low-Power Pedestrian Detection System on FPGA
Proceedings, 2019 Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection.
Vinh Ngo +4 more
doaj +1 more source
LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA
Xibei Gongye Daxue Xuebao, 2019 A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase ...
doaj +1 more source
Design of FPGA Speech Ｒecognition Four Ｒotor Aircraft Control System
Journal of Harbin University of Science and Technology, 2017 This paper uses FPGA speech recognition command as the four-rotor aerial remote control command． The FPGA can quickly process information combined voice control of the simple，accurate and flexible features． The control system is divided into two parts．
JING Gu, ZHANG Xue-song
doaj +1 more source
Hierarchical reconfiguration of FPGAs [PDF]
2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014 Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules.
Christian Beckhoff, Dirk Koch
openaire +4 more sources
Brain‐Inspired In‐Memory Data Pruning and Computing with TaOx Mem‐Selectors
Advanced Materials, EarlyView.In article number 2502168, Zhongrui Wang, Xiaoxin Xu, Dashan Shang, and co‐workers present the first nanoscale Mem‐Selector device that integrates both nonvolatile resistive memory and volatile threshold switching functionalities for visual data pruning.
Yi Li +15 more
wiley +1 more source
Scientific ReportsIn the field of Brain Machine Interface (BMI), the process of translating motor intention into a machine command is denoted as decoding. However, despite recent advancements, decoding remains a formidable challenge within BMI.
Danial Katoozian +2 more
doaj +1 more source
Design and development of SHINE accelerator fast interlock system
He jishuBackgroundShanghai HIgh repetitioN rate XFEL and Extreme light facility (SHINE) is a large-scale scientific facility under construction in China. Due to 1 MHz repetition rate and thousands of kilometers length of SHINE, the accelerator interlock system ...
YU Chunlei +5 more
doaj +1 more source
Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence [PDF]
, 2013 This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry
Arslan, Tughrul +5 more
core +2 more sources