Results 281 to 290 of about 85,934 (320)

An area efficient gate-all-around ring MOSFET

2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016
This paper proposes an area efficient gate-all-around ring (GAAR) MOSFET structure for vertical integration, which in essence is an arc-shaped double-gate FinFET and gains benefits of the superior gate control in GAA MOSFETs and feasible manufacturability.
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang   +2 more
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CMOS-compatible gate-all-around silicon nanowire detector

2011 IEEE SENSORS Proceedings, 2011
In this paper, we demonstrate gate-all-around (GAA) single crystalline nanowires (SiNWs) that are fabricated using top-down standard CMOS front-end processes. The GAA silicon nanowires are fabricated in well-defined locations with high-quality electrical contacts, and controlled geometry and alignment.
Maryam Ziaei-Moayyed, Murat Okandan
openaire   +1 more source

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

ECS Transactions, 2022
A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an I on/I off ...
Junk, Yannik, Liu, Mingshan, Frauenrath, Marvin, Hartmann, Jean-Michel, Gruetzmacher, Detlev, Buca, Dan, Zhao, Qing-Tai   +6 more
openaire   +1 more source

From Gate-all-Around to Nanowire MOSFETs

2007 International Semiconductor Conference, 2007
The classical MOSFET is reaching its scaling limits and "end-of-roadmap" alternative devices are being investigated. Amongst the different types of SOI devices proposed, one clearly stands out: the multigate field-effect transistor (multigate FET). This device has a general "wire-like" shape.
openaire   +1 more source

Device Simulation on Gate-All-Around Cylindrical Transistor

2010 International Conference on System Science, Engineering Design and Manufacturing Informatization, 2010
In this paper, we reported TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10 nm scaling. The GAAC transistor device physics, TCAD simulation have been discussed. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET ...
Deyuan Xiao, Xi Wang, Jing Chen, Xiaolu Huang, Jiexin Luo, Qingqing Wu   +5 more
openaire   +1 more source

AFM characterization for Gate-All-Around (GAA) devices

Metrology, Inspection, and Process Control for Microlithography XXXIV, 2020
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the ...
Mary A. Breton, Jennifer Fullam, Lan Yu, Dexin Kong, Daniel Schmidt, Andrew Greene, Liying Jiang, Sean Hand, Jason Osborne   +8 more
openaire   +1 more source

Buckling characterization of gate all around silicon nanowires

SPIE Proceedings, 2013
Imaging of suspended silicon nanonwires (SiNW) by SEM reveals that some of the SiNW are buckled. Buckling can impact device performance and it is therefore important to characterize this phenomenon. Measuring the buckling of suspended silicon nanowires (SiNW) poses significant challenges: (1) Small dimensions - SiNW are made with diameters ranging from
Shimon Levi, Ishai Schwarzband, Yakov Weinberg, Roger Cornell, Ofer Adan, Guy M. Cohen, Cheng Cen, Lynne Gignac   +7 more
openaire   +1 more source

Characteristics of GaN-Based Nanowire Gate-All-Around (GAA) Transistors

Journal of Nanoscience and Nanotechnology, 2020
We investigate the DC, C–V, and pulse performances in GaN-based nanowire gate-all-around (GAA) transistors with two kinds of geometry: one is AlGaN/GaN heterostructure with two dimensional electron gas (2DEG) channel and the other is only GaN layer without 2DEG channel.
Ki-Sik, Im, Mallem Siva Pratap, Reddy, Jinseok, Choi, Youngmin, Hwang, Jea-Seung, Roh, Sung Jin, An, Jung-Hee, Lee   +6 more
openaire   +2 more sources

Gate-all-around silicon nanowire MOSFETs and circuits

68th Device Research Conference, 2010
We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I
J. W. Sleight, S. Bangsaruntip, A. Majumdar, G. M. Cohen, Y. Zhang, S. U. Engelmann, N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. M. Frank, J. Chang, M. Guillorn   +12 more
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Gate-all-around Twin Silicon nanowire SONOS Memory

2007 IEEE Symposium on VLSI Technology, 2007
We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mus at Vd = 2 V, Vg = 6 V and erase speed of 1 ms at Vd = 4.5 V, Vg = -6 V are achieved with 2~3 nm nanowire and 30 nm gate.
Sung Dae Suk, Kyoung Hwan Yeo, Keun Hwi Cho, Ming Li, Yun young Yeoh, Ki-Ha Hong, Sung-Han Kim, Young-Ho Koh, Sunggon Jung, WonJun Jang, Dong-Won Kim, Donggun Park, Byung-Il Ryu   +12 more
openaire   +1 more source