Results 291 to 300 of about 85,934 (320)
Some of the next articles are maybe not open access.
SiGe Gate-All-around Nanosheet Reliability
2022 IEEE International Reliability Physics Symposium (IRPS), 2022Huimei Zhou +5 more
openaire +1 more source
Silicon-on-insulator 'gate-all-around' MOS device
1990 IEEE SOS/SOI Technology Conference. Proceedings, 2002The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the
J.-P. Colinge +4 more
openaire +1 more source
Si nanowire MOSFET with gate-all-around electrode
2009 International Semiconductor Device Research Symposium, 2009Beyond 2011, when the channel length of a MOSFET transistor is projected to be 16 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 16 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge.
C. Ndoye +6 more
openaire +1 more source
High threshold voltage matching performance on gate-all-around MOSFET
Solid-State Electronics, 2006Abstract For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on Gate-All-Around transistors (GAA) with both doped and undoped channels. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants.
Cathignol, A. +8 more
openaire +1 more source
Gate-All-Around Technology is Coming.
Proceedings of the 2023 International Symposium on Physical Design, 2023openaire +1 more source
Localized thermal effects in Gate-all-around devices
2023 IEEE International Reliability Physics Symposium (IRPS), 2023Colin Landon +6 more
openaire +1 more source
Gate-All-Around Technology for Harsh Environment Applications
2002Gate-Ail-Around (GAA) transistors are thin, fully depleted SOI MOSFETs with a double gate structure. When used at high temperature GAA devices present low leakage current, minimal threshold voltage shift and, in general, better characteristics than bulk or even SOI MOSFETs.
openaire +1 more source
Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications
ACS Applied Materials & Interfaces, 2021Yiheng Yin, Zhaofu Zhang, Hongxia Zhong
exaly

