Results 271 to 280 of about 85,934 (320)

(Invited) Gate-All-Around Ge FETs

ECS Meeting Abstracts, 2014
Abstract- High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced Ion of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls and subthreshold characteristics of 94 mV/dec. The JL Ge GAA pFETs with fin width (Wfin) down to 27 nm and
C. W. Liu, Yen-Ting Chen, Shu-Han Hsu
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Ge gate-all-around FETs on Si

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
High performance Ge inversion (INV) and junctionless (JL) gate-all-around (GAA) FETs are demonstrated on epi-Ge layer on SOI. The anisotropic etching is used to remove the defect near the Ge/Si interface and to form gate-all-around structure. The INV and JL pGAAFETs have I on of 235 µA/µm and 270 µA/µm at V GS − V T = −2 V and V DS = −1 V ...
C. W. Liu, null I-Hsieh Wong, null Yen-Ting Chen, null Wen-Hsien Tu, null Shih-Hsien Huang, null Shu-Han Hsu   +5 more
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Radiation effects in gate-all-around structures

1991 IEEE International SOI Conference Proceedings, 2002
Gate-all-around (GAA) devices have been characterized by current vs. voltage techniques after being exposed to 10-keV X-rays under a variety of bias conditions. Parameters such as mobility, oxide trapped charge, interface state density, and leakage currents were monitored. The SIMOX (separation by implanted oxygen) GAA device, which has no buried-oxide
R.K. Lawrence, J.P. Colinge, H.L. Hughes
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Gate-All-Around Silicon Nanowire Transistor Technology

2020
As a promising alternative to the fundamental device structure, the gate-all-around silicon nanowire transistor (GAA SNWT) has been studied extensively for decades. In this chapter, the device physics, compact modeling, and fabrication process of GAA SNWT are systematically reviewed, as well as its potential applications in terms of different ...
Ru Huang, Runsheng Wang, Ming Li
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Modeling of Nanoscale Gate-All-Around MOSFETs

IEEE Electron Device Letters, 2004
We present a compact physics-based model for the nanoscale gate-all-around MOSFET working in the ballistic limit. The current through the device is obtained by means of the Landauer approach, being the barrier height the key parameter in the model. The exact solution of the Poisson's equation is obtained in order to deal with all the operation regions ...
D. Jimenez, J.J. Saenz, B. Iniguez, J. Sune, L.F. Marsal, J. Pallares   +5 more
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Germanium Gate-All-Around pFETs on SOI

ECS Transactions, 2013
The triangular Ge GAA pFET was fabricated and simulated. The hole concentration was obtained from spreading resistance profiling (SRP) and used in the simulation. Device with fin width (Wfin) of 52nm and Lg of 183nm has Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 μA/um at Vd= -1V.
Hung-Chih Chang, S.-H Hsu, C.-L Chu, Y.-T Chen, W.-H Tu, P.-J Sung, G.-Li Luo, Y. –C. Yin Yin, C. W. Liu   +8 more
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Silicon-on-insulator 'gate-all-around device'

International Technical Digest on Electron Devices, 2002
Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing.
J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. Maes, C. Claeys   +4 more
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Gate-all-around technology: Taking advantage of ballistic transport?

Solid-State Electronics, 2009
Abstract This work presents an experimental study in order to evaluate the quality of transport in the most advanced state-of-the-art gate-all-around devices in term of performances. Experiments have been done on silicon channel devices with metal/high-k gate all-round stack at aggressive dimensions (L × W × TSi = 25nm × 20 nm × 10nm).
J.L., Huguenin, Bidal, G., Denorme, S., Fleury, D., Loubet, N., Pouydebasque, A., Perreau, P., Leverd, F., Barnola, S., Beneyton, R., Orlando, B., Gouraud, P., Salvetat, T., Clement, L., Monfray, S., Ghibaudo, G., Boeuf, F., Skotnicki, T.   +17 more
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Gate-All-Around Nanopore Osmotic Power Generators

ACS Nano
Nanofluidic channels in a membrane represent a promising avenue for harnessing blue energy from salinity gradients, relying on permselectivity as a pivotal characteristic crucial for inducing electricity through diffusive ion transport. Surface charge emerges as a central player in the osmotic energy conversion process, emphasizing the critical ...
Makusu Tsutsui, Wei-Lun Hsu, Denis Garoli, Iat Wai Leong, Kazumichi Yokota, Hirofumi Daiguji, Tomoji Kawai   +6 more
openaire   +3 more sources

Lateral gate-all-around (GAA) poly-Si transistors

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2002
High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabricated using a novel technique for crystallization of a-Si.
P. Kalavade, K.C. Saraswat
openaire   +1 more source