Hardware implementation of memristor-based artificial neural networks [PDF]
Nature CommunicationsArtificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel.
Fernando Aguirre +30 more
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Compressive Sensing Image Sensors-Hardware Implementation [PDF]
Sensors, 2013 The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image ...
Shahram Shirani +2 more
doaj +5 more sources
Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks. [PDF]
Nat Commun, 2023 Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them.
Kim IJ, Kim MK, Lee JS.
europepmc +2 more sources
Hardware implementation of Bayesian network based on two-dimensional memtransistors. [PDF]
Nat Commun, 2022 Bayesian networks (BNs) find widespread application in many real-world probabilistic problems including diagnostics, forecasting, computer vision, etc.
Zheng Y +5 more
europepmc +2 more sources
Full hardware implementation of neuromorphic visual system based on multimodal optoelectronic resistive memory arrays for versatile image processing. [PDF]
Nat Commun, 2023 In-sensor and near-sensor computing are becoming the next-generation computing paradigm for high-density and low-power sensory processing. To fulfil a high-density and efficient neuromorphic visual system with fully hierarchical emulation of the retina ...
Zhou G +12 more
europepmc +2 more sources
Digital Image Decoder for Efficient Hardware Implementation [PDF]
Sensors, 2022 Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression.
Goran Savić +3 more
doaj +2 more sources
An adaptive threshold neuron for recurrent spiking neural networks with nanodevice hardware implementation. [PDF]
Nat Commun, 2021 We propose a Double EXponential Adaptive Threshold (DEXAT) neuron model that improves the performance of neuromorphic Recurrent Spiking Neural Networks (RSNNs) by providing faster convergence, higher accuracy and a flexible long short-term memory.
Shaban A, Bezugam SS, Suri M.
europepmc +2 more sources
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis [PDF]
Sensors, 2020 In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding ...
Riccardo Peloso +5 more
doaj +2 more sources
Hardware Implementation for Triaxial Contact-Force Estimation from Stress Tactile Sensor Arrays: An Efficient Design Approach [PDF]
SensorsThis paper presents a contribution to the state of the art in the design of tactile sensing algorithms that take advantage of the characteristics of generalized sparse matrix-vector multiplication to reduce the area, power consumption, and data storage ...
María-Luisa Pinto-Salamanca +2 more
doaj +2 more sources
Energy-efficient Mott activation neuron for full-hardware implementation of neural networks. [PDF]
Nat Nanotechnol, 2021 Oh S +8 more
europepmc +2 more sources