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On hardware-in-the-loop simulation
Proceedings of the 44th IEEE Conference on Decision and Control, 2006Hardware-in-the-loop simulation is a well established technique used in design and evaluation of control systems. The purpose of this paper is twofold. First it aims to identify research questions related to the design of hardware-in-the-loop simulation.
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Loop pipelining in hardware-software partitioning
Proceedings of 1998 Asia and South Pacific Design Automation Conference, 1998This paper presents a hardware-software partitioning algorithm that exploits a loop pipelining technique. The partitioning algorithm is based on iterative improvement. The algorithm tries to minimize hardware cost through hardware sharing and hardware implementation selection without violating given performance constraint.
Jinhwan Jeon, Kiyoung Choi
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Hardware-in-Loop Assessment of Control Architectures
2020 24th International Conference on System Theory, Control and Computing (ICSTCC), 2020This paper proposes a method of testing by simulation of automatic control solutions of manufacturing processes that are performed on a mechatronic laboratory line. The method is based on the use of Digital Twin technology and allows the evaluation by simulation of both the hardware infrastructure of the controllers (Hardware in the Loop simulation ...
Radu Dobrescu +4 more
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A micro Hardware-In-the-Loop test system
2009 European Control Conference (ECC), 2009Automotive companies commonly adopt Hardware-In-the-Loop simulators to develop new control strategies in order to reduce the effort and the cost of the testing phase. The engine management system is an important component of actual road vehicles, it has a vital impact on fuel economy and reduced emissions.
Angelo Palladino +3 more
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Quantifying the Accuracy of Hardware-in-the-Loop Simulations
2007 American Control Conference, 2007In this paper we present a methodology for quantifying the accuracy of hardware-in-the-loop (HWIL) simulators. HWIL simulation refers to the process of interfacing a subset of system hardware to a controller containing a numerical model of the rest of the system.
Monte Stuart MacDiarmid, Marko Bacic
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Hardware pipelining of runtime-detected loops
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 2012Dynamic partitioning is a promising technique where computations are transparently moved from a General Purpose Processor (GPP) to a coprocessor during application execution. To be effective, the mapping of computations to the coprocessor needs to consider aggressive optimizations.
João Bispo +2 more
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Interface Compensation for Power Hardware-in-the-Loop
2018 IEEE 27th International Symposium on Industrial Electronics (ISIE), 2018Power Hardware-in-the-Loop (PHIL) is a real-time system testing and validation technique particularly attractive for large scale power systems. The key challenge is achieving a transparent power interface between the simulation and the physical Item-under- Test (Iu‘I’), Signal exchange between the systems is defined by the interface algorithm (IA), and
Nathan D. Marks +2 more
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Hardware-in-the-Loop Simulation
2012This chapter describes the application of real-time, hardware-in-the-loop (HIL) simulation for hydropower plant. This mode of simulation is a powerful tool for upgrading high-value plant that carries a severe financial penalty for loss of service. The concept and merits of HIL simulation and the distinctive features of real-time systems are reviewed ...
German Ardul Munoz-Hernandez +2 more
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Hardware in loop testing of an insulin pump
2015 IEEE International Test Conference (ITC), 2015System test plays a very important role in the product development cycle of a safety-critical device, such as an insulin pump. Given the significant risk of this device, fault-injection should be performed to validate dependable implementation under abnormal circumstances, namely: data corruption, bit flips, incorrect signal assertions and more ...
Sriram Karunagaran +2 more
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Loop transformations leveraging hardware prefetching
Proceedings of the 2018 International Symposium on Code Generation and Optimization - CGO 2018, 2018Memory-bound applications heavily depend on the bandwidth of the system in order to achieve high performance. Improving temporal and/or spatial locality through loop transformations is a common way of mitigating this dependency. However, choosing the right combination of optimizations is not a trivial task, due to the fact that most of them alter the ...
Savvas Sioutas +4 more
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