Results 201 to 210 of about 706 (250)
Some of the next articles are maybe not open access.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
This paper explores a variation of the Han-Carlson adder for large word sizes and compares the performance of the new design with the traditional design. This work introduces a second type of design with two Brent-Kung stages each at the beginning and at the end and with Kogge-Stone stages in the middle, henceforth referred to as the “Hybrid Han ...
Sreenivaas Muthyala Sudhakar +2 more
openaire +2 more sources
This paper explores a variation of the Han-Carlson adder for large word sizes and compares the performance of the new design with the traditional design. This work introduces a second type of design with two Brent-Kung stages each at the beginning and at the end and with Kogge-Stone stages in the middle, henceforth referred to as the “Hybrid Han ...
Sreenivaas Muthyala Sudhakar +2 more
openaire +2 more sources
Energy efficient hybrid adder architecture
Integration, 2015An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition.
Shmuel Wimer, Amnon Stanislavsky
openaire +1 more source
A hybrid ling carry-select adder
Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004., 2005Hybrid adders, combining a sparse carry-lookahead tree and a carry-select output stage are a well-known implementation form of high-speed adders. In this paper, a hybrid Ling carry-select adder is presented. It is shown how a carry-select output stage can be used to eliminate the entire conversion of all pseudo-carries.
J. Grad, J.E. Stine
openaire +1 more source
Design of 4-BIT ripple carry adder using hybrid 9TFull adder
2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015], 2015In this paper a hybrid GDI based 9T full adder and 4-bit ripple carry adder (RCA) are designed, which reduces power consumption and area of digital circuits while maintaining low complexity of logic design. The proposed full adder and RCA has been designed in MICROWIND environment with 0.12μm technology.
S. Usha, T. Ravi
openaire +1 more source
Analysis of High Speed Hybrid Full Adder
2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS), 2021Multiplier plays an important role in the design of FIR filters in digital signal processors (DSP). In VLSI the multipliers performance speed affects the overall speed of the system. Moreover, multiplication process uses execution time in most of the DSP devices. Hence, high speed is required in multiplier.
V. Vijayakumar +3 more
openaire +1 more source
Implementation of Carry Save Adder Using Novel Eighteen Transistor Hybrid Full Adder
2020 International Conference on Power Electronics and Renewable Energy Applications (PEREA), 2020A novel 1-bit hybrid full adder circuit is implemented using eighteen transistors. Simulations are done using the Cadence Virtuoso Schematic Editor in 180 and 90 nm technologies. The performances are evaluated based on its speed, average power consumption, and power-delay product.
Saina Ancy Simon, Sujithamol. S
openaire +1 more source
Design of a Hybrid Adder in QCA
2015In the previous chapter, we presented efficient QCA realizations of existing adders based on new results on majority logic.
K. Sridharan, Vikramkumar Pudi
openaire +1 more source
Hybrid adders for high-speed arithmetic circuits: A comparison
2010 7th International Conference on Electrical Engineering Computing Science and Automatic Control, 2010In this paper the most interesting topologies of one-bit hybrid full adders, are analyzed and compared for speed, power consumption, and power-delay product. The investigation has been carried out with properly defined simulation set up and input pattern on a Mentor Graphics environment using a TSMC 180 nm CMOS process.
Mónico Linares Aranda +2 more
openaire +1 more source
A low-power high-speed hybrid full adder
2016 20th International Symposium on VLSI Design and Test (VDAT), 2016In this paper we present a new hybrid FA design (mix of CMOS and pass transistor logic styles), which aims at achieving higher speed but keeping power dissipation low, and hence targeting low PDP. Our proposed FA and seven other existing FA designs are simulated in spice, using 45 nm low power model file, using standard test bed and test pattern (56 ...
Manan Mewada, Mazad Zaveri
openaire +1 more source
Fast hybrid parallel carry look-ahead adder
Optics Letters, 1990A new optical parallel arithmetic processing scheme using a nonholographic optoelectronic content-addressable memory (CAM) is discussed. The design of a four-bit CAM-based optical carry look-ahead adder (CLA) is presented. Compared with existing optoelectronic binary addition approaches, this nonholographic CAM scheme offers a number of practical ...
A, Kostrzewski +3 more
openaire +2 more sources