Results 211 to 220 of about 706 (250)
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Approximate Adder with Hybrid Prediction and Error Compensation Technique
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016This paper proposed an approximate adder to accelerate computation and reduce energy consumption for error-resilient applications with a moderate output quality losses. The computation acceleration comes from the predictionscheme for the adder circuit, where the critical path is divided into multiple short fragments and a paralleling addition progress ...
Xinghua Yang +4 more
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Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019One of the critical issues in the advancement of very large scale of integration circuit design is the estimation of timing behavior of the arithmetic circuits. The concept of logical effort provides a proficient approach to comprehend and assess the timing behavior of circuits with conventional CMOS (C-CMOS) structure.
Hareesh-Reddy Basireddy +2 more
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Hybrid Variable Latency Carry Skip Adder
2018 International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET), 2018The hybrid variable latency carry skip adder (HVL-CSKA) is obtained by structural modification of the concatenation and incrementation scheme carry skip adder (CI-CSKA). CI-CSKA uses AND-OR-INVERT (AOI) logic and OR-AND-INVERT (OAI) logic as the skip logic instead of multiplexers as in the conventional carry skip adder.
Signa Jom, J. Asha
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Low Power 14T Hybrid Full Adder Cell
2017The performance of the adder entirely influenced by the performance of its basic modules. In this paper, a new hybrid 1-bit 14 transistor full adder design is proposed. The proposed circuit has been implemented using pass gate as well as CMOS logic hence named hybrid.
Chauhan Sugandha, Sharma Tripti
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A recursive carry-lookahead/carry-select hybrid adder
IEEE Transactions on Computers, 1993The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes, Jr.'s spanning tree carry lookahead adder or redundant cell adder (see ibid., vol. 41, 1992) which was implemented using the Am29050 microprocessor.
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Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime
International Conference on Nanoscience, Engineering and Technology (ICONSET 2011), 2011This paper presents an implementation of two 8-bit adders (HPA and CIA) and comparing their performance with respect to power delay product for different voltages in 90 nm regime. HPA is derived from Parallel prefix adders for minimized Power Delay product.
A. N. Nagamani, B. K. Shivanand
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Design and Performance Comparison Analysis of Hybrid Adders
Engineering and Applied Science, 2012Adder cell using Pass Transistor Logic (PTL) and Gate Diffusion Technique (GDI) is been described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant ...
Rajkumar Sarma, Jyotirmoy Pathak
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Fast Low-Power 64-Bit Modular Hybrid Adder
2005This paper presents the design of a new dynamic addition circuit based on a hybrid ripple-carry/carry-look-ahead/carry-bypass approach. In order to reduce power, the usage of duplicated carry-select stages is avoided. High computational speed is reached thanks to the implemented two-phase running. The latter makes the proposed adder able to exploit the
PERRI, Stefania +2 more
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A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL
Journal of Circuits, Systems and Computers, 2011A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability.
Reza Faghih Mirzaee +3 more
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Review and Implementation of 1-Bit Adder in CMOS and Hybrid Structures
2020Different adder structures have been reviewed with CMOS logic and hybrid logic styles in this paper. XOR/XNOR cell, which is the key element in full adder design was also reviewed. Hybrid adders have advantage of low delay and low area occupancy due to less transistor count used. Lower value of PDP also can be achieved with hybrid structures.
Bhaskara Rao Doddi, V. Leela Rani
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