Results 221 to 230 of about 706 (250)

Low Power Scalable Ternary Hybrid Full Adder Realization

2020 32nd International Conference on Microelectronics (ICM), 2020
Multi-level electronic systems offer speed and area simplicity, reducing the complexity of implementation and power dissipation. In this paper, a Hybrid ternary Full Adder (FA) is proposed using Conventional Complementary Metal Oxide Semiconductor (CCMOS), Double Pass-transistor Logic (DPL), and Pass Transistors (PT).
Mohamed S. Ghoneim, Amr Mohammaden, Rana Hesham, Ahmed H. Madian   +3 more
openaire   +1 more source

Low power multipliers based on new hybrid full adders

Microelectronics Journal, 2008
Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors.
Zine Abid, Hayssam El-Razouk, Dalia A. El-Dib   +2 more
openaire   +1 more source

A High-Performance Hybrid Full Adder Circuit

2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2022
Md. Shahbaz Hussain, Jyoti Kandpal, Mohd Hasan, Mohd Muqeem   +3 more
openaire   +1 more source

Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

IETE Journal of Research, 2023
Thamizharasan V
exaly  

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

International Journal of Circuit Theory and Applications, 2021
Mainul Hossain, Sharnali Islam, Mehedi Hasan   +2 more
exaly  

Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

IETE Journal of Research, 2023
Ganesh Babu C, Dinesh Kumar J R
exaly  

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

Computer Systems Science and Engineering, 2023
B. Annapoorani, P. Marikkannu
openaire   +1 more source

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

International Journal of Electronics, 2023
Thamizharasan V
exaly  

Searching for Energy-Efficient Hybrid Adder-Convolution Neural Networks

2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), 2022
Wenshuo Li, Xinghao Chen 0001, Jinyu Bai, Xuefei Ning, Yunhe Wang 0001   +4 more
openaire   +1 more source

Design and Analysis of an Approximate Adder with Hybrid Error Reduction

Electronics (Switzerland), 2020
Yoon Seok Yang, Yongtae Kim, Hyoju Seo
exaly