Results 31 to 40 of about 1,515,607 (318)
Automatic Vectorization Transplant and Optimization of LLVM for Domestic Processors [PDF]
Jisuanji gongcheng, 2022 Automatic vectorization is essential in SIMD extension vectorization, and has been implemented in the LLVM compiler.However, the difference of vector length and instruction set functions can cause the domestic processors to lose the opportunity of ...
LI Jia'nan, HAN Lin, CHAI Yunda
doaj +1 more source
Machine Assisted Proof of ARMv7 Instruction Level Isolation Properties [PDF]
, 2013 In this paper, we formally verify security properties of the ARMv7 Instruction Set Architecture (ISA) for user mode executions. To obtain guarantees that arbitrary (and unknown) user processes are able to run isolated from privileged software and other ...
A. Fox +6 more
core +2 more sources
Software-Based Self-Test of Set-Associative Cache Memories [PDF]
, 2011 Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set ...
Di Carlo, Stefano +2 more
core +1 more source
On-Line Instruction-checking in Pipelined Microprocessors [PDF]
, 2008 Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges.
Di Carlo, Stefano +2 more
core +2 more sources
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue [PDF]
, 2006 The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots.
Abella Ferrer, Jaume +1 more
core +1 more source
Instruction Set Architectures for Quantum Processing Units
, 2017 Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows.
AR Calderbank +3 more
core +1 more source
Pediatric Blood &Cancer, EarlyView.ABSTRACT The pediatric hematology‐oncology fellowship training curriculum has not substantially changed since its inception. The first year of training is clinically focused, and the second and third years are devoted to scholarship. However, this current structure leaves many fellows less competitive in the current job market, resulting in ...
Scott C. Borinstein +3 more
wiley +1 more source
Pediatric Blood &Cancer, EarlyView.ABSTRACT Introduction We developed MedSupport, a multilevel medication adherence intervention designed to address root barriers to medication adherence. This study sought to explore the feasibility and acceptability of the MedSupport intervention strategies to support a future full‐scale randomized controlled trial.
Elizabeth G. Bouchard +8 more
wiley +1 more source
Compiler Optimization of Wide Memory Access for Aarch64
Современные информационные технологии и IT-образованиеThe popularity of ARM-based processors in HPC and cloud computing is gradually increasing and the development of compilers and code optimizations is important to achieve better use of hardware resources.
Viacheslav Chernonog +2 more
doaj +1 more source
Design and Implementation of RISC-Ⅴ Extended Ⅰnstruction Set Supporting FPGA Dynamic Reconfiguration [PDF]
Jisuanji gongchengCurrently, dynamic refactoring is implemented by configuring it through on-chip interfaces, usually using the dynamic refactoring control Intellectual Property (IP) core provided by the official Field Programmable Gate Array (FPGA), and connected to the ...
ZHOU Xuanjin, CAI Gang, HUANG Zhihong
doaj +1 more source