Results 31 to 40 of about 8,185,322 (352)
Sensors, 2017 For an inductive wireless power transfer (IWPT) system, maintaining a reasonable power transfer efficiency and a stable output power are two most challenging design issues, especially when coil distance varies.
Zhidong Miao, Dake Liu, Chen Gong
doaj +1 more source
Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension
Acoustics, 2022 As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom ...
Jun Yuan +5 more
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Instruction set compiled simulation [PDF]
Proceedings of the 40th annual Design Automation Conference, 2003 Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator.
Prabhat Mishra +2 more
openaire +1 more source
On algorithmic equivalence of instruction sequences for computing bit string functions [PDF]
, 2014 Every partial function from bit strings of a given length to bit strings of a possibly different given length can be computed by a finite instruction sequence that contains only instructions to set and get the content of Boolean registers, forward jump ...
Bergstra, J. A., Middelburg, C. A.
core +2 more sources
A scalable ASIP for BP Polar decoding with multiple code lengths
MATEC Web of Conferences, 2018 In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates.
Qiao Wan, Liu Dake
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Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
Cryptography, 2022 The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı +2 more
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Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models [PDF]
, 2010 The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide ...
A. Peymandoust +56 more
core +3 more sources
Frontiers in Psychology, 2022 To examine the effects of combined positive verbal encouragement and general technical guidelines on technical and psychophysiological parameters in pupils during a small-sided handball passing game.
Feten Sahli +8 more
doaj +1 more source
On Architectural Support for Instruction Set Randomization [PDF]
ACM Transactions on Architecture and Code Optimization, 2020 Instruction Set Randomization (ISR) is able to protect against remote code injection attacks by randomizing the instruction set of each process. Thereby, even if an attacker succeeds to inject code, it will fail to execute on the randomized processor.
Christou, George +4 more
openaire +3 more sources
A complete formal semantics of x86-64 user-level instruction set architecture
ACM-SIGPLAN Symposium on Programming Language Design and Implementation, 2019 We present the most complete and thoroughly tested formal semantics of x86-64 to date. Our semantics faithfully formalizes all the non-deprecated, sequential user-level instructions of the x86-64 Haswell instruction set architecture.
Sandeep Dasgupta +4 more
semanticscholar +1 more source