Results 31 to 40 of about 1,478,008 (318)
Frontiers in Psychology, 2022 To examine the effects of combined positive verbal encouragement and general technical guidelines on technical and psychophysiological parameters in pupils during a small-sided handball passing game.
Feten Sahli +8 more
doaj +1 more source
Quantum Instruction Set Design for Performance
Physical Review Letters, 2023 2 figures in main text and 21 figures in Supplementary Materials. This manuscript subsumes version 1 with significant improvements such as experimental demonstration and materials ...
Cupjin Huang +12 more
openaire +3 more sources
On Architectural Support for Instruction Set Randomization [PDF]
ACM Transactions on Architecture and Code Optimization, 2020 Instruction Set Randomization (ISR) is able to protect against remote code injection attacks by randomizing the instruction set of each process. Thereby, even if an attacker succeeds to inject code, it will fail to execute on the randomized processor.
Christou, George +4 more
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Characteristics of simulations for instructional settings [PDF]
Education and Computing, 1991 This paper discusses the internal characteristics of simulations. The major part of it is concerned with models and their relation with the domain. Some central concepts regarding modelling and simulation are defined. These include concepts regarding:- the structure and characteristics of the model;- the relationship to the system that is being ...
Ton de Jong, Wouter R. van Joolingen
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Function-call Instruction Characteristic Analysis Based Instruction Set Architecture Recognization Method for Firmwares [PDF]
Jisuanji kexueThe recognition of instruction set architecture is a crucial task for conducting security research on embedded devices,and has significant implications.However,existing studies and tools often suffer from low recognition accuracy and high false positive ...
JIA Fan, YIN Xiaokang, GAI Xianzhe, CAI Ruijie, LIU Shengli
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Software-Based Self-Test of Set-Associative Cache Memories [PDF]
, 2011 Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set ...
Di Carlo, Stefano +2 more
core +1 more source
Machine Assisted Proof of ARMv7 Instruction Level Isolation Properties [PDF]
, 2013 In this paper, we formally verify security properties of the ARMv7 Instruction Set Architecture (ISA) for user mode executions. To obtain guarantees that arbitrary (and unknown) user processes are able to run isolated from privileged software and other ...
A. Fox +6 more
core +2 more sources
On-Line Instruction-checking in Pipelined Microprocessors [PDF]
, 2008 Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges.
Di Carlo, Stefano +2 more
core +2 more sources
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue [PDF]
, 2006 The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots.
Abella Ferrer, Jaume +1 more
core +1 more source
Canadian Journal of Academic Librarianship, 2023 In academic libraries, library instruction often takes the form of one-shot instruction and is not always deeply linked to the broader curricula. This article will argue that if library instruction in an academic setting is to be perceived as beneficial
Roberto Arteaga
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