Results 101 to 110 of about 3,728 (141)

Inverse Lithography Technology (ILT): what is the impact to the photomask industry?

SPIE Proceedings, 2006
Inverse Lithography Technology (ILT) is a rigorous approach to determine the mask shapes that produce the desired on-wafer results. In this paper, we briefly describe an image (or pixel))-based implementation of ILT in comparison to OPC technologies, which are usually edge-based.
Linyong Pang
exaly   +2 more sources

Inverse lithography technology at low k1: placement and accuracy of assist features

SPIE Proceedings, 2006
An implementation of inverse lithography technology is studied with special attention to illustrating and analyzing the placement, accuracy, and efficacy of subresolution assist elements. One-dimensional placement through pitch is characterized, and 2D capability is demonstrated for repeated patterns.
Linyong Pang
exaly   +2 more sources

Validation of inverse lithography technology (ILT) and its adaptive SRAF at advanced technology nodes

Proceedings of SPIE, 2008
In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices.
Linyong Pang, Grace Dai, Tom Cecil
exaly   +2 more sources

Inverse lithography technology: verification of SRAM cell pattern

SPIE Proceedings, 2005
Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD measurements.
Artur Balasinski, Andrew Moore, Nader Shamma, Timothy Lin, Hee-hong Yang   +4 more
openaire   +2 more sources

Evaluation of inverse lithography technology for 55nm-node memory device

SPIE Proceedings, 2008
Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC.
Byung-ug Cho, Sung-woo Ko, Jae-seung Choi, Cheol-Kyun Kim, Hyun-jo Yang, DongGyu Yim, David Kim, Bob Gleason, KiHo Baik, Ying Cui, Thuc Dam, Linyong Pang   +11 more
openaire   +2 more sources

Manufacturability study of masks created by inverse lithography technology (ILT)

SPIE Proceedings, 2005
As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes ...
Patrick M. Martin, C. J. Progler, G. Xiao, R. Gray, L. Pang, Y. Liu   +5 more
openaire   +2 more sources

Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)

Proceedings of SPIE, 2008
Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during lithography optimization and RET application is essential to obtain a usable process window (PW).
Linyong Pang, Guangming Xiao, Vikram Tolani   +2 more
exaly   +2 more sources

Enhancing DRAM printing process window by using inverse lithography technology (ILT)

SPIE Proceedings, 2006
Inverse lithography technology (ILT) was studied during process development for four layers from memory semiconductor designs. This paper describes techniques used in each of the layers. So as to demonstrate this technology in a wide range of semiconductor patterns, we show results from all four layers.
Linyong Pang
exaly   +2 more sources

First 65nm tape-out using inverse lithography technology (ILT)

SPIE Proceedings, 2005
This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength ...
Chi-Yuan Hung, Bin Zhang, Deming Tang, Eric Guo, Linyong Pang, Yong Liu, Andrew Moore, Kechang Wang   +7 more
openaire   +2 more sources

Robust level-set-based inverse lithography [PDF]

Optics Express, 2011
Level-set based inverse lithography technology (ILT) treats photomask design for microlithography as an inverse mathematical problem, interpreted with a time-dependent model, and then solved as a partial differential equation with finite difference ...
Yijiang Shen, Ningning Jia, Ngai Wong
exaly   +2 more sources