Results 121 to 130 of about 168 (150)

Inverse lithography technology at chip scale

SPIE Proceedings, 2006
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We discuss some specifics of ILT at chip-scale. We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing results from ILT-generated masks and OPC-generated masks for ...
Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Orson Lin, Jason Lin, Yong Liu, Linyong Pang   +10 more
openaire   +1 more source

Hot-Spots Aware Inverse Lithography Technology

ECS Transactions, 2009
This paper presents a new method of Inverse Lithography Technology (ILT) to accelerate its optimization process and convergence, which involves two steps in iteration: the first step is to find hot-spots in the layout in the optimization process and the second step is to optimize on the hot-spot areas.
Yiwei Yang, Zheng Shi, Shanhu Shen, Chunlei Xie   +3 more
openaire   +1 more source

Inverse lithography technology: verification of SRAM cell pattern

SPIE Proceedings, 2005
Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD measurements.
Artur Balasinski, Andrew Moore, Nader Shamma, Timothy Lin, Hee-hong Yang   +4 more
openaire   +1 more source

Seamless-merging-oriented parallel inverse lithography technology

Journal of Semiconductors, 2009
Inverse lithography technology (ILT), a promising resolution enhancement technology (RET) used in next generations of IC manufacture, has the capability to push lithography to its limit. However, the existing methods of ILT are either time-consuming due to the large layout in a single process, or not accurate enough due to simply block merging in the ...
Yang Yiwei, Shi Zheng, Shen Shanhu
openaire   +1 more source

Advanced memory cell design optimization with inverse lithography technology

Design-Process-Technology Co-optimization for Manufacturability XIV, 2020
Memory cells and access structures consume a large percentage of area in embedded devices so there is a high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements.
Jiro Higuchi, Weiting Wang, Takamasa Takaki, Hiromitsu Mashita, Shigeki Nojima, Ahmed S. Omran, Ken Hanafusa, Seung-Hee Baek, Ryan Chen, Yukio Asaka, Kyle Braam, Hironobu Taoka, Guangming Xiao   +12 more
openaire   +1 more source

A new algorithm of inverse lithography technology for mask complexity reduction

Journal of Semiconductors, 2012
A new complexity penalty term called the global wavelet penalty is introduced, which evaluates the high-frequency components of masks more profoundly by applying four distinctive Haar wavelet transforms and choosing the optimal direction on which the highest frequency components of the mask will be removed.
Yanghuan Li, Zheng Shi, Zhen Geng, Yiwei Yang, Xiaolang Yan   +4 more
openaire   +1 more source

SRAF rule extraction and insertion based on inverse lithography technology

Optical Microlithography XXXII, 2019
The placement and size of SRAF (sub-resolution assisted feature) can greatly affect the overlapped process window. The time-consuming inverse lithography technology (ILT) can provide the co-optimization for both main pattern and SRAFs, which can guarantee the results with high precision.
Xiaojing Su, Pengzheng Gao, Yayi Wei, Weijie Shi   +3 more
openaire   +1 more source

A Mask Generation Approach to Double Patterning Technology with Inverse Lithography

Japanese Journal of Applied Physics, 2008
Pattern reduction has generated much interest in developing effective methods of reducing the feature sizes of microelectronic and data-storage devices. For below-32-nm node technology, the bottom-up approach, namely, self-assembly, has obstacles such as the insufficient support of processes and mass production, and the top-down approaches, namely ...
Sang-Kon Kim, Hye-Keun Oh, Young-Dae Jung, Ilsin An   +3 more
openaire   +1 more source

Manufacturability study of masks created by inverse lithography technology (ILT)

SPIE Proceedings, 2005
As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes ...
Patrick M. Martin, C. J. Progler, G. Xiao, R. Gray, L. Pang, Y. Liu   +5 more
openaire   +1 more source

Inverse Lithography Technology (ILT) Enabled Source Mask Optimization (SMO)

ECS Transactions, 2009
In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask.
Linyong Pang, Guangming Xiao, Vikram Tolani, Peter Hu, Tom Cecil, Thuc Dam, Ki-Ho Baik, Bob Gleason   +7 more
openaire   +1 more source