Results 171 to 180 of about 3,543 (201)

A novel trench gate LDMOS

2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2004
In this paper a novel trench gate lateral double diffused MOSFET (TG-LDMOS) device will be discussed and compared to the conventional LDMOS structure. Currently, the LDMOS devices are the preferred technology for base station amplifiers and in Power MOSFET switching applications.
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LDMOS–SCR: a replacement for LDMOS with high ESD self-protection ability for HV application

Semiconductor Science and Technology, 2012
A study of LDMOS–SCR devices for SOI BCD technology is presented. The LDMOS–SCR is fully compatible with BCD process and can replace the LDMOS as a high voltage output driver. By comparison of the LDMOS and another 'pnpn' type of LDMOS–SCR, the triggering mechanism and ESD behavior are well discussed with both device simulation and TLP measurement.
Peng Zhang, Yuan Wang, Song Jia, Xing Zhang   +3 more
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120 V super junction LDMOS transistor

2013 IEEE International Conference of Electron Devices and Solid-state Circuits, 2013
Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars.
Sumit Kumar Panigrahi, Usha Gogineni, Maryam Shojaei Baghini, Farshid Iravani   +3 more
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Hot-carrier reliability in OPTVLD-LDMOS

Journal of Semiconductors, 2012
An improved structure that eliminates hot-carrier effects (HCE) in optimum variation lateral doping (OPTVLD) LDMOS is proposed. A formula is proposed showing that the surface electric field intensity of the conventional structure is strong enough to make a hot-carrier injected into oxide.
Junji Cheng, Xingbi Chen
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TCAD degradation modeling for LDMOS transistors

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012
Physically-based models of hot-carrier stress and dielectric field-enhanced thermal damage have been incorporated in the framework of a TCAD tool with the aim of investigating the electrical stress degradation in integrated power devices over an extended range of stress biases and ambient temperatures.
REGGIANI, SUSANNA, BARONE, GAETANO, GNANI, ELENA, GNUDI, ANTONIO, S. Poli, M. Y. Chuang, W. Tian, R. Wise   +7 more
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A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018
In this paper, a simple p-LDMOS structure with significantly improved performances based on a novel three dimensional concept is proposed. The hole current in the Ptop region of the signal region flows into the floating P+, then through the integrated resistor R p formed by the Pbase region in the z-axis direction with a distance of W 2 +W 3 , into ...
Bo Yi, Junji Cheng, Moufu Kong, Bingke Zhang, Xing Bi Chen   +4 more
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InGaAs LDMOS power semiconductor device performances

2009 International Conference on Power Electronics and Drive Systems (PEDS), 2009
An n-channel In 0.65 Ga 0.35 As LDMOS with Al 2 O 3 as gate dielectric is proposed. Power device parameters such as specific on-resistance, gate charge, and breakdown voltage are examined using two-dimensional device simulation. Comparison between In 0.65 Ga 0.35 As Si devices is made.
Liu, Yidong, Yuan, Jiann Shiun, Steighner, Jason   +2 more
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Lateral thinking about power devices (LDMOS)

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 2002
BiCMOS Power technology LDMOS are reviewed with respect to category and structure definition and briefly as to how the structures relate to figure of merit performance. Stepped gate oxide devices are introduced making use of popular dual gate technologies and exhibit improved R/sub sp/ vs.
T.R. Efland, null Chin-Yu Tsai, S. Pendharkar   +2 more
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Modeling high power RF LDMOS amplifiers

2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535), 2004
This paper focuses on the package model extraction methodology and large signal model verification of high power RF LDMOS amplifiers. Results validating the extracted package models are presented. Accurate models of the power amplifier that also allow for simulations of the linearity aspects, such as IMD3 and IMD5 is presented.
K. Goverdhanam, J. Lott, S. Moinian, null Ru Li, J. Zell, S. Perelli, null Wenhua Dai, M. Frei, D. Farrell, D.A. Bell, E. Lau   +10 more
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A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

Chinese Physics B, 2013
A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SOI) p-channel lateral double-diffused metal—oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLDMOS ...
Kun Zhou, Xiao-Rong Luo, Yuan-Hang Fan, Yin-Chun Luo, Xia-Rong Hu, Bo Zhang   +5 more
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