Results 211 to 220 of about 49,541 (265)

Wireplanning in logic synthesis

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98, 1998
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deep submicron technologies. We first show that conventional logic synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli   +3 more
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Logic synthesis for testability

Proceedings of the Sixth Great Lakes Symposium on VLSI, 1996
This paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit.
Chien-Chung Tsai, Malgorzata Marek-Sadowska   +1 more
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Synthesis of Logic Interpretations

2016 IEEE 17th International Symposium on High Assurance Systems Engineering (HASE), 2016
Logic interpretations define the relationships between real-world entities and their logic representations. We introduce an explicit structure for documenting interpretations based on real-world types. As we have demonstrated previously, the benefits of using real-world types can be considerable, but the effort required might deter programmers. In this
Jian Xiang, John C. Knight, Kevin J. Sullivan   +2 more
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Logic synthesis for manufacturability

IEEE Design and Test of Computers, 2004
Design optimization during synthesis is for area and/or performance while optimization for yield occurs at the layout level. To obtain abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis.
Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli   +1 more
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A logic for synthesis design

Tetrahedron, 1981
Abstract The background for synthesis design logic is presented, followed by the development of a procedure aimed at assessing all and locating the best synthetic routes. The procedure has two stages, first a dissection of skeleton, then a generation of necessary functionality on it to afford successive construction reactions.
JAMES B. HENDRICKSON, ELAINE BRAUN-KELLER, GLENN A. TOCZKO   +2 more
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Logic synthesis with constraints

Microprocessing and Microprogramming, 1988
Abstract Recent work in logic synthesis [Bra83], [Bra87a], [Bra87b] has resulted in the development of efficient algorithms for organizing and optimizing networks of logic expressions. A number of synthesis systems based on these or similar algorithms have been devised [Bar86], [The87], [Bra86]. In these, logic synthesis is performed in two stages:
A. Fox, C. T. Spracklen, C. P. Jolly
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The role of learning in logic synthesis

[Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence, 1990
The goal of logic synthesis is to obtain high-quality designs from specifications. Current approaches to logic synthesis often trade off design quality for technology independence. In this paper, we present a model of logic synthesis that uses technology-specific design rules and extends rule-based search to functional decomposition and technology ...
James R. Kipps, Daniel D. Gajski
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Technology adaption in logic synthesis

Proceedings of the 23rd ACM/IEEE conference on Design automation - DAC '86, 1986
Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements, from Boolean minimizers to procedures attempting to satisfy a wider range of criteria. Gate or cell count, taken as a measure of area, continues to be a major factor in design acceptability, but timing constraints, testability ...
William H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen   +4 more
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Logic synthesis at Sun

Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, 2003
A description is given of Sun's experiences as an early user of the Synopsys tools and the results of some experiments evaluating and comparing commercial logic synthesis tools. The behavior of the algorithms is discussed along with areas where the tools could be improved. >
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Logic transformations for synchronous logic synthesis

Twenty-Third Annual Hawaii International Conference on System Sciences, 2002
An approach to logic synthesis of digital synchronous sequential circuits is presented. Algorithms are described for minimizing the area of synchronous combinational and/or sequential circuits under cycle time constraints and for minimizing the cycle time under area constraints.
G. De Micheli, R. Yip
openaire   +1 more source