Results 221 to 230 of about 49,541 (265)
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Proceedings of the seventeenth design automation conference on Design automation - DAC '80, 1980
Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization.
John A. Darringer, William H. Joyner Jr.
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Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization.
John A. Darringer, William H. Joyner Jr.
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Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.
Robert K. Brayton, Sunil P. Khatri
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We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.
Robert K. Brayton, Sunil P. Khatri
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Metrics for structural logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design - ICCAD '02, 2002Routability or wiring congestion in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the ...
Prabhakar Kudva +2 more
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2006
It is unlikely that we will be able to utilize the full potential of VLSI without major improvements in designer productivity. One approach is to design at a higher functional level and to generate acceptable implementations automatically from such functional specifications.
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It is unlikely that we will be able to utilize the full potential of VLSI without major improvements in designer productivity. One approach is to design at a higher functional level and to generate acceptable implementations automatically from such functional specifications.
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Circuit partitioning for logic synthesis
IEEE Journal of Solid-State Circuits, 1991The authors introduce a circuit partitioning method based on analysis of reconvergent fan-out. A corolla is defined as a set of overlapping reconvergent fan-out regions. The authors partition the circuit into a set of disjoint corollas and use the corollas to resynthesize the circuit.
Sujit Dey, Franc Brglez, Gershon Kedem
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Logic synthesis for programmable logic design
Proceedings of WESCON '94, 2002This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) based on either the Verilog HDL or VHDL. It describes aspects of synthesis and optimization specific to FPGAs and CPLDs, in contrast to CMOS gate-arrays.
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Proceedings of the 1985 ACM thirteenth annual conference on Computer Science - CSC '85, 1985
John A. Darringer +4 more
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John A. Darringer +4 more
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Pragmatics in the Synthesis of Logic Programs
1999Many of the systems which we, and those who have worked with us, have built were intended to make it easier for people with particular backgrounds to construct and understand logic programs. A major issue when designing this sort of system is pragmatics: from the many logically equivalent ways of describing a program we must identify styles of ...
David Stuart Robertson 0001 +1 more
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Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004
Abhinav Agrawal 0002, Niraj K. Jha
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Abhinav Agrawal 0002, Niraj K. Jha
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