Results 121 to 127 of about 22,185 (127)

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs

Journal of Circuits, Systems and Computers, 2019
A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables.
Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski   +2 more
openaire   +1 more source

Verticalization Of Direct Structural Table In Synthesis Of Mealy FSMS For FPGAs

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., 2006
The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits
A. Bukowiec, A. Barkalov
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OPTIMIZATION OF MEALY FSM CIRCUIT IN MIXED ELEMENT BASIS

KIBERNETYKA TA SYSTEMNYI ANALIZ
A method of reducing LUT count in the FPGA-based circuit of Mealy finite state machine (FSM). A part of the circuit is implemented using embedded memory block (EMB). The method is based on the twofold state assignment and encoding collections of microoperations. An example of the synthesis of FSM circuit using the proposed method is given. When certain
A.A. Barkalov, L.A. Titarenko, O.M. Golovin, A.V. Matviienko   +3 more
openaire   +1 more source

Synthesis of mealy FSM with multiple shared encoding of microinstructions and internal states

IFAC Proceedings Volumes, 2006
Abstract The method of hardware optimization of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the encoding identifiers, representing pairs (next state;microinstruction), for all suhtables of direct structural tahle of FSM.
openaire   +1 more source

Design of CPLD-based mealy FSMs with counters

2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2018
Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski   +2 more
openaire   +2 more sources

Object Codes Transformation for Mealy FSMs

2015
Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo   +4 more
openaire   +1 more source

Designing LUT-based mealy FSMs with transformation of state codes

AIP Conference Proceedings, 2017
Kamil Mielcarek, Alexander Barkalov, Larisa Titarenko   +2 more
openaire   +1 more source