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Improving Temporal Characteristics of Mealy FSM with Composite State Codes

Electronics
In this paper, we proposed a new state assignment method focusing on Mealy finite state machines (FSMs). The method makes it possible to improve the temporal characteristics of the circuits of FSMs, the internal states of which are encoded by the composite state codes (CSCs). These codes consist of class codes and partial state codes.
Larysa Titarenko, Kazimierz Krzywicki, Oleksandr Barkalov   +2 more
exaly   +3 more sources

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EMB - based design of Mealy FSM

IFAC Postprint Volumes IPPV / International Federation of Automatic Control, 2013
Abstract A method is proposed allowing implementing Mealy FSM logic circuits with embedded memory blocks of FPGA chips. The method is based on transformation of FSM structure table and replacement of some logical conditions. Example of design and results of investigations are given.
Larysa Titarenko, Alexander Barkalov
exaly   +3 more sources

Reducing LUT Count for Mealy FSMs With Transformation of States

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
Modern digital systems can be viewed as compositions of combinational and sequential blocks. In the article, we discuss a case when sequential blocks are represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption.
Larysa Titarenko, Oleksandr Barkalov, Kamil Mielcarek   +2 more
exaly   +2 more sources

Hardware reduction for EMB-based Mealy FSM

IFAC-PapersOnLine, 2015
Abstract A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given.
Larysa Titarenko, Marek Wegrzyn, Alexander Barkalov   +2 more
exaly   +2 more sources

Optimization for Logic Circuit of Mealy FSM

Lecture Notes in Electrical Engineering, 2009
The chapter is devoted to the hardware amount reduction in the logic circuit of Mealy FSM. The methods of logical condition replacement are analyzed, as well as different methods of encoding of collections of microoperations (maximal encoding and encoding of the classes of compatible microoperations).Next, the methods of structure table rows encoding ...
Larysa Titarenko, Alexander Barkalov
exaly   +2 more sources

Reducing hardware in FPGA-based Mealy FSM

Proceedings of SPIE, 2017
This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results
Larysa Titarenko, Kamil Mielcarek, Alexander Barkalov   +2 more
exaly   +2 more sources

Design of FPGA-based Mealy FSMs with Counters

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES), 2018
A method is proposed for hardware reduction of FPGA-based Mealy FSM's logic circuit. The method is based on replacement of state register by state counter. The content of the counter can be increased during both conditional and unconditional transitions. There is an example of application of proposed method.
Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski   +3 more
openaire   +2 more sources

Encoding of Terms in LUT-based Mealy FSMs

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES), 2018
A method is proposed for hardware reduction in FPGA-based Mealy FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.
Larysa Titarenko, Kamil Mielcarek, Alexander Barkalov   +2 more
exaly   +3 more sources

Synthesis of Mealy FSMs with Counters

2020
The Chapter is devoted to the using linear chains in Mealy FSMs. The known counter-based models of Moore FSMs are discussed together with corresponding design methods. Then, there are proposed models and design methods for counter-based Mealy FSMs. There are proposed synthesis methods based on natural and extended linear chains of states.
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski   +3 more
openaire   +1 more source

Twofold State Assignment for Mealy FSMs

2020
The chapter begins from the general idea of twofold state assignment for Mealy FSMs. The method is based on partitioning the set of states by classes. Each internal state is encoded in two ways: as an element of the set of FSM states and as an element of some class of states. It allows implementing any function for a given class using only a single LUT.
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski   +3 more
openaire   +1 more source