Results 61 to 70 of about 21,543 (210)

Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

open access: yes, 2006
Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations.
Ashburn, P.   +6 more
core  

Low‐Dimensional Materials and Van Der Waals Heterostructures for Energy Application: A Comprehensive Review

open access: yesENERGY &ENVIRONMENTAL MATERIALS, EarlyView.
Low‐dimensional materials (0D, 1D, and 2D) exhibit unique electronic and physicochemical properties, enabling advanced nanoelectronic and optoelectronic devices. Mixed‐dimensional heterostructures combine these materials to enhance functionality.
Qaisar Alam   +3 more
wiley   +1 more source

The impact of random doping effects on CMOS SRAM cell [PDF]

open access: yes, 2004
The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs.
Cheng, B., Asenov, A., Roy, S.
core   +1 more source

Wide‐Bandgap Semiconductor‐Based Neuromorphic Computing

open access: yesInformation &Functional Materials, EarlyView.
Wide‐bandgap semiconductors enable robust, low‐power neuromorphic devices for extreme environments. This review outlines material advantages, device physics, integration, and future directions for next‐generation brain‐inspired computing. ABSTRACT Neuromorphic computing has emerged as a promising paradigm to overcome the energy inefficiency and data ...
Hongyu Tang   +6 more
wiley   +1 more source

Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation

open access: yes, 2003
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their oayout, which is considerably larger than for a lateral MOSFET on the
Ashburn, Peter   +11 more
core  

Exploding Bridgewire (EBW) Detonators: An Example of Synergistic Multiphysics

open access: yesPropellants, Explosives, Pyrotechnics, EarlyView.
ABSTRACT Exploding bridgewire (EBW) detonators are highly temporally reproducible explosive devices that require the rapid discharge of a high‐voltage capacitance to operate and so are immune to most of the accidental hazards associated with traditional electric detonators.
P. J. Rae   +3 more
wiley   +1 more source

Compact modelling in RF CMOS technology [PDF]

open access: yes, 2011
With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years.
Liu, Jun
core  

Advances in Gate Dielectrics for 2D Electronics

open access: yesphysica status solidi (RRL) – Rapid Research Letters, EarlyView.
This review discusses advanced gate dielectric integration for 2D electronic devices, including layered and nonlayered dielectric materials, while highlighting strategies such as seed‐assisted ALD, transfer methods, and in situ oxidation. By focusing on interface engineering and materials innovation, new routes for scalable, high‐performance 2D ...
Moon‐Chul Jung   +2 more
wiley   +1 more source

Synthesis of Amorphous‐Crystalline Mixture Boron Nitride for Balanced Resistive Switching Operation

open access: yesSmall, EarlyView.
An amorphous–crystalline mixture BN (acm‐BN) is synthesized through low‐pressure chemical vapor deposition, achieving balanced resistive switching with low SET voltage and stable RESET. High‐resolution transmission electron microscopy reveals that BN films are fully amorphous at 930 °C, a mixed amorphous–crystalline phase is achieved at 990 °C.
Kyung Jin Ahn   +8 more
wiley   +1 more source

Unified Steep‐Slope Switching and Non‐Volatile Memory in a Complementarily Stabilized van der Waals Ferroelectric Transistor

open access: yesSmall, EarlyView.
We present a van der Waals FeNC‐FET that simultaneously achieves sub‐60 mV/dec steep switching and non‐volatile memory within a single transistor. A CIPS/h‐BN/α‐In2Se3 bi‐ferroelectric gate stack enables a stabilized negative‐capacitance state in FE1 while maintaining the bistable polarization of FE2.
Sangmin Lee   +5 more
wiley   +1 more source

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