Results 81 to 90 of about 28,940 (205)

Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation

, 2003
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their oayout, which is considerably larger than for a lateral MOSFET on the
Ashburn, Peter, Hall, Steven, Donaghy, David C., Uchino, Takashi, Hemment, Peter L F, Kunz, V Dominik, Hemment, P. L. F., Donaghy, David C, De Groot, C. H. (Kees), de Groot, C.H.(Kees), Wang, Yun, Kunz, V. Dominik   +11 more
core   +1 more source

Self‐Driving Laboratory Optimizes the Lower Critical Solution Temperature of Thermoresponsive Polymers

Advanced Intelligent Discovery, EarlyView.
A low‐cost, self‐driving laboratory is developed to democratize autonomous materials discovery. Using this "frugal twin" hardware architecture with Bayesian optimization, the platform rapidly converges to target lower critical solution temperature (LCST) values while self‐correcting from off‐target experiments, demonstrating an accessible route to data‐
Guoyue Xu, Renzheng Zhang, Tengfei Luo
wiley   +1 more source

Temperature‐Tunable Cholesteric Liquid Crystal Optical Combiners for Extended Reality Applications

Advanced Intelligent Systems, Volume 7, Issue 3, March 2025.
Recent advancements in extended reality highlight their potential to enhance traditional displays like liquid crystal displays and organic light‐emitting diode screens. This article introduces an innovative cholesteric liquid crystal‐based optical combiner for head‐mounted displays, enabling seamless transitions between augmented reality, virtual ...
Yuanjie Xia, Haobo Li, Marija Vaskeviciute, Daniele Faccio, Affar S. Karimullah, Hadi Heidari, Rami Ghannam   +6 more
wiley   +1 more source

Fabrication and characterisation of novel Ge MOSFETs [PDF]

As high-k dielectrics are introduced into commercial Si CMOS (Complimentary Metal Oxide Semiconductor) microelectronics, the 40 year channel/dielectric partnership of Si/SiO2 is ended and the door opened for silicon to be replaced as the active channel ...
Beer, Chris
core  

Electrical Characteristics of Single, Double and Surround Gate Vertical MOSFETs with Reduced Overlap Capacitance

, 2003
The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50nm. Surround gate structures can be realised which offer improved short channel effects and more channel with per unit silicon area. In this paper, a
Uchino, T, Donaghy, D, Ashburn, P, Gili, E, de Groot, C H, Hall, S, Kunz, V D   +6 more
core   +1 more source

Physics‐Grounded Probabilistic Bits for Hardware‐Efficient Intelligent Inference and Optimization

Advanced Intelligent Systems, EarlyView.
Si–SiNx interface traps are harnessed as a complementary metal–oxide–semiconductor‐compatible source of controllable randomness for probabilistic bits. Pulse‐width‐programmed stochastic capture converts nanoscale defect dynamics into Boltzmann‐consistent binary outputs, while a physics‐based Simulation Program with Integrated Circuit Emphasis model ...
Dokyoung Lee, Jun‐Young Park, Joon‐Kyu Han, Sungho Kim   +3 more
wiley   +1 more source

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation [PDF]

, 2005
Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs.
Samsudin, K., Cheng, B., Brown, A.R., Asenov, A., Roy, S., A. Asenov, A.R. Brown, B. Cheng, S. Roy, K. Samsudin   +9 more
core   +1 more source

A Generalizable Framework for Building Executable Domain‐Specific Large Language Models Under Data Scarcity: Demonstration on Semiconductor Technology Computer‐Aided Design Simulation

Advanced Intelligent Systems, EarlyView.
A schema‐first alignment framework builds compact, executable domain‐specific language models under data scarcity. Large‐scale synthetic question‐answer generation instills domain knowledge, and a code‐centric IR‐to‐DPO pipeline aligns generation with tool‐executable syntax.
Di Wang, Zhenhua Wu, Yu Liu, Kai Chang, Shaohua Wu   +4 more
wiley   +1 more source

Bayesian Optimization–Reinforcement Learning Hybrid Framework for a‐IGZO Thin‐Film Transistor Compact Model Parameter Extraction in 2T0C Dynamic Random Access Memory Applications

Advanced Intelligent Systems, EarlyView.
A training‐free two‐stage BO–RL framework extracts compact model parameters for a‐IGZO TFTs, reaching BO‐level fitting quality at a constant per‐simulation optimization cost. Bayesian optimization performs exploration and provides an optimized starting point.
Seunghyun Son, Taejun Ha, Taeyoung Nam, Yoonyoung Chung, Sunmean Kim   +4 more
wiley   +1 more source

Active voltage balancing by turn‐off delays regulation for multiple series‐connected SiC MOSFETs

IET Power Electronics
SiC MOSFETs are currently the most appropriate solution for high‐efficiency conversions at low kilovolts (
Cédric Mathieu de Vienne, Pierre Lefranc, Pierre‐Olivier Jeannin, Bruno Lefebvre, Besar Asllani   +4 more
doaj   +1 more source