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Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Xiaochen Guo +2 more
exaly
Hard Error Correction in STT-MRAM
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)Surendra Hemaram +5 more
openaire +1 more source

