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A Framework for Automated Reasoning in Multiple-Valued Logics

Journal of Automated Reasoning, 1998
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James J. Lu, Neil V. Murray, Erik Rosenthal   +2 more
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Multiple-valued logic design tools

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic, 2002
A brief overview of past progress in multiple-valued logic design is presented. The methods are considered with respect to the likely development of multiple-valued field programmable gate arrays. Look-up table based arrays are considered in some detail and an algorithm for mapping multiple-valued functions to such an array is presented. This algorithm
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Multiple valued logic for microprocessors

Euromicro Newsletter, 1980
Abstract Pin limitation has always been an important problem of Integrated Circuits Packages. In this paper, we examine multiple valued logic as an alternative approach to time multiplexing. TTL and CMOS 4-2 and 2–4 interface circuits are presented and it is shown that 4-valued address, data and coded control lines would solve most of pin limitation ...
D. Etiemble, J.P. Aillaud
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Multiple-Valued Logic: An Introduction and Overview

IEEE Transactions on Computers, 1977
MULTIPLE-VALUED logic has been a subject of research work for many years [1], [2]. Until the late 1960's most of the reported work was of a theoretical nature, leaving little impact on the firmly established binary approaches in the design of digital systems.
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A non-commutative multiple-valued logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic, 2002
A set of operations which can be used to design n-valued switching functions is given. These give rise to a class of algebras which are left-handed skew lattices together with dual implication operation. Such algebras form a decidable discriminator variety, and hence possess a well-behaved structure theory and satisfy many identities.
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Multiple-valued logic in FPGAs

Proceedings of 36th Midwest Symposium on Circuits and Systems, 2002
This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of field-programmable gate arrays (FPGAs). It proposes an FPGA logic block architecture that features MVL current-mode CMOS circuitry. The logic block combines the lookup-table and multiplexer approaches found in commercial FPGAs, and provides additional ...
Z. Zilic, Z.G. Vranesic
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Development of Programmable Logic Array for Multiple-Valued Logic Functions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
The binary information technology reaches its limits set by the atomic size miniaturization, by calculation speed and by the fundamental principle of energy dissipation per bit processing. Employing multiple-valued logic (MVL) cells as computing and memory units reduces energy losses and enables to pack of unprecedented high-density information, but ...
Vitaly G. Levashenko, Igor Lukyanchuk, Elena Zaitseva, Miroslav Kvassay, Jan Rabcan, Patrik Rusnak   +5 more
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Multiple-Valued Logic: An Implementation

Optical Engineering, 1986
The state of the art for multiple-valued electronic devices relying on integrated injection logic (I2L) is discussed. Applications and extension of multiple-valued I2L devices to quaternary logic technology are presented.
T. T. Dao, D. M. Campbell
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Conquering Uncertainty in Multiple-Valued Logic Design

Artificial Intelligence Review, 2003
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Automated Deduction in Multiple-valued Logics

1994
Abstract This book constitutes a self-contained and unified approach to automated reasoning in multiple-valued logics (MVL) developed by the author. Moreover, it contains a virtually complete account of other approaches to automated reasoning in MVL. This is the first overview of this subfield of automated reasoning ever given.
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