Enabling scalable ferroelectric-based future generation vertical NAND flash with bonding-friendly architecture: strategies for erase and disturb optimization. [PDF]
Song I, Kim J, Lee S, Myeong I.
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Advancing the Frontiers of HfO<sub>2</sub>-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]
Zhou Z +9 more
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Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash. [PDF]
Hwang H, Kim G, Yu D, Kim H.
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Band and Field Coengineered Charge Trap Memristor via Au Nanoparticle Layer for Programming Speed Enhancement. [PDF]
Kim G +6 more
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Hafnium-Based Ferroelectric Post-Moore Electronics: Device Physics, Integration Architectures, and Neuromorphic System Implementation. [PDF]
Chen X, Wang Z, Meng J, Wang T.
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Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories. [PDF]
Refaldi DG +4 more
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Ferroelectric NAND for efficient hardware bayesian neural networks. [PDF]
Song M +10 more
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A full-featured 2D flash chip enabled by system integration. [PDF]
Liu C +13 more
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Recent advances in ferroelectric materials, devices, and in-memory computing applications. [PDF]
Hwang H, Youn S, Kim H.
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The data archiving in the small herbaria digitisation workflow. [PDF]
Novikov A.
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