Results 101 to 110 of about 10,811 (199)

Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference. [PDF]

Micromachines (Basel), 2021
Yi SI, Kim J.
europepmc   +1 more source

GSFC Annual Scan Technology Review SpaceCube On-Board Processor Update [PDF]

No abstract ...
Wilson, Christopher
core   +1 more source

A machine learning framework for predictive electron density modelling to enhance 3D NAND flash memory performance

e-Prime: Advances in Electrical Engineering, Electronics and Energy
Data storage in electronic devices has been revolutionised by 3D NAND flash memory. However, polycrystalline silicon and grain boundaries offer issues that greatly affect memory performance in terms of string current and Program-Erase Threshold Voltage ...
Dikendra Verma, Upendra Mohan Bhatt, Anurag Vidyarthi   +2 more
doaj   +1 more source

CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory. [PDF]

Sci Adv, 2021
Kim MK, Kim IJ, Lee JS.
europepmc   +1 more source

Intelligent Read Framework With Meta-Learning for NAND Flash Memory Under Process Variation

IEEE Access
The storage density of NAND flash memory has significantly increased due to multi-leveling and downscaling technologies. As a side effect of enhanced storage capacity, flash memory becomes vulnerable to circuit-level noise.
Minyoung Hwang, Inhyuk Choi, Jeongju Jee, Hyuncheol Park   +3 more
doaj   +1 more source

Prediction of Random Telegraph Noise-Induced Threshold Voltage Shift and Its Scaling Dependency Using Machine Learning

IEEE Journal of the Electron Devices Society
Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced ${\mathrm { V}}_{\mathrm { t}}$ shift in
Eunseok Oh, Hyungcheol Shin
doaj   +1 more source

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme. [PDF]

Front Neurosci, 2020
Lee ST, Lee JH.
europepmc   +1 more source

Memorie Flash a NAND

In questa tesi verranno trattate le memorie Flash. Partendo da una breve introduzione all'argomento, si studierà prima il funzionamento a livello fisico del transistor, il suo inserimento in un'architettura a NAND e i metodi di accesso e scrittura del dati in tale contesto.
openaire   +1 more source

Dynamic pass bias control for temperature-resilient neural networks using vertical NAND flash memory. [PDF]

Nano Converg
Park SH, Im J, Ko J, Hwang J, Yang Y, Back JW, Koo RH, Lee IS, Shin D, Oh M, Jung G, Lee JH.   +11 more
europepmc   +1 more source