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Flash Watermark: An Anticounterfeiting Technique for NAND Flash Memories
IEEE Transactions on Electron Devices, 2020This article demonstrates a novel technique for watermarking commercial off-the-shelf NAND flash memory chips. The technique uses repeated program-erase stressing to selectively control the physical properties of the flash cells and hence imprint watermark information into the flash media in an irreversible manner.
Sadman Sakib +2 more
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Extended Word-Line NAND Flash Memory
Japanese Journal of Applied Physics, 2009A NAND flash memory array having extended word-lines is proposed. Without scarifying areal density, both physical gate length and charge storage node size are increased through the word-line extension process. Simple fabrication flow is delivered and device performances in a viewpoint of the short channel effect are simulated. The effect of gate length
Jang-Gn Yun +4 more
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Flash new laws [NAND flash memory circuits]
Electronics Systems and Software, 2007The rapid growth in NAND flash capacity has made it possible to store hundreds of thousands of images from high-end digital still cameras. But the most recent increases in claimed capacity are coming at the expense of increased die size. The Samsung 64 Gb NAND flash memory was built using a technique called self-aligned double-patterning in an attempt ...
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NAND Flash Memory: Challenges and Opportunities
Computer, 2013NAND flash offers a range of compelling benefits that will keep attracting mobile and enterprise application developers as engineers tackle the hard problems of scaling the technology to sub-20 nm.
Yan Li, Khandker N. Quader
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TID Sensitivity of NAND Flash Memory Building Blocks
IEEE Transactions on Nuclear Science, 2008NAND Flash memories are the leader among high capacity non-volatile memory technologies and are becoming attractive also for radiation harsh environments, such as space. For these applications, a careful assessment of their sensitivity to radiation is needed.
BAGATIN, MARTA +5 more
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Single Event Effects in NAND Flash Memory Arrays
IEEE Transactions on Nuclear Science, 2005We are showing for the first time the charge loss due to heavy ion irradiation on Flash memory arrays organized following the NAND architecture. Results complement those previously found for devices featuring a NOR architecture: large charge loss can be expected after the hit of a single ion on a single memory cell.
G. Cellere +4 more
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Neuromorphic Technology Utilizing Nand Flash Memory Cells
2020 China Semiconductor Technology International Conference (CSTIC), 2020Hardware-based neural networks are expected to be a new computing breakthrough beyond conventional von Neumann architecture because of their low power operations. In this work, we introduce operation scheme of neural networks using NAND flash memory cell as analogue and binary-state synaptic devices.
Sung-Tae Lee, Jong-Ho Lee
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Evolution of NAND Flash Memory Interface
2007In this paper, we describe the basics of NAND flash memory and describe the evolution of its interface to facilitate easy integration, to provide high bandwidth, to offer disk-like interface, and/or to guarantee interoperability.
Sang Lyul Min +2 more
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Reliability issues of NAND Flash memories
2010The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view.
C. Zambelli, A. Chimenton, P. Olivo
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3D Floating Gate NAND Flash Memories
2016Planar NAND Flash memories (commercially available) are based on Floating Gate, which has been developed and engineered for many decades. Therefore, there have been many attempts to develop 3D Floating Gate cells in order to re-use all the know-how cumulated over time.
Rino Micheloni, Luca Crippa
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