Results 211 to 220 of about 29,727 (252)

Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
This paper summarizes the scaling challenges of the conventional 2D floating-gate cell NAND flash memories [1, 2]. The scaling trends and limits of the bulk and SOI NAND flash memories are investigated in terms of short channel effects and channel boosting leakage from 20nm to below 10nm generation using 3D-device simulation.
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Exploring modeling and testing of NAND flash memories

2010 East-West Design & Test Symposium (EWDTS), 2010
Testing NAND flash memories is a very complex issue due to the rapid scaling down of the technology and the related floating gate reliability issues: as a consequence a complete and technology independent test is needed. Several faults and disturbances were identified both for NOR and NAND flash memories: however they has never been considered together
DI CARLO, STEFANO, Fabiano, M., Piazza, R., PRINETTO, Paolo Ernesto   +3 more
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An Abstract Fault Model for NAND Flash Memory

IEEE Embedded Systems Letters, 2012
We present an abstract fault model for NAND flash memory that describes precisely the effects of various faults during a flash operation. The abstract model is intended to be used to reason about fault-related correctness of key modules of flash memory management software such as a flash translation layer (FTL).
JiHyuck Yun, Jinhyuk Yoon, Eyee Hyun Nam, Sang Lyul Min   +3 more
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Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory

IEEE transactions on computers, 2020
By stacking layers vertically, the adoption of 3D NAND has significantly increased the capacity for storage systems. The complex structure of 3D NAND introduces more errors than planer flash.
Qiao Li, Liang Shi, Yufei Cui, C. Xue
semanticscholar   +1 more source

A superblock-based flash translation layer for NAND flash memory

Proceedings of the 6th ACM & IEEE International conference on Embedded software - EMSOFT '06, 2006
In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL)is usually employed to hide the erase-before-write characteristics of NAND flash memory. This paper proposes a novel superblockbased FTL scheme, which combines a set of adjacent logical blocks into a superblock.
Jeong-Uk Kang, Heeseung Jo, Jinsoo Kim 0001, Joonwon Lee   +3 more
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A visual approach to interpreting NAND flash memory

Digital Investigation, 2014
The research described in this paper proposes methods for visually interpreting the content of raw NAND flash memory images into higher level visual artefacts of assistance in reverse engineering and interpreting flash storage formats. A novel method of reverse engineering the structure and layout of individual memory locations within NAND flash images,
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Modeling NAND Flash Memories for Circuit Simulations

2007
In this paper, we will present the basic structure and the parameter extraction procedure for a compact model of a NAND Flash memory string working in Spicelike circuit simulators. To the author knowledge, this is the first Spice-like model of a NAND Flash memory string. This model is modular and simple to be implemented.
LARCHER, Luca, PADOVANI, ANDREA, I. RIMMAUDO, PAVAN, Paolo, A. CALDERONI, G. MOLTENI, F. GATTEL, P. FANTINI   +7 more
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Empirical evaluation of NAND flash memory performance

ACM SIGOPS Operating Systems Review, 2010
Reports of NAND ash device testing in the literature have for the most part been limited to examination of circuit-level parameters on raw ash chips or prototypes, and system-level parameters on entire storage subsystems. However, there has been little examination of system-level parameters of raw devices, such as mean latency and endurance values.
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3D Stacked NAND Flash Memories

2016
Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time

IEEE International Solid-State Circuits Conference, 2018
Wooseong Cheong, Chanho Yoon, Simon S. Woo, K.-H. Han, Daehyun Kim, Chul Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jae-Beom Park, Ki-Whan Song, Ki-Tae Park, Sangyeun Cho, H. Oh, Daniel D. G. Lee, Jin-Hyeok Choi, Jaeheon Jeong   +18 more
semanticscholar   +1 more source