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Characterization of Inter-Cell Interference in 3D NAND Flash Memory

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2021
We characterize inter-cell interference in commercial three-dimensional NAND flash memory. By writing random data into 3D NAND and collecting sample means and sample variances of cell values corresponding to a particular set of input values in fixed ...
Sukkwang Park, J. Moon
semanticscholar   +1 more source

High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling

IEEE transactions on computers
In the age of artificial intelligence, large language models (LLM) require rapid development along with massive volumes of training data and parameter storage.
Guangkuo Yang   +10 more
semanticscholar   +1 more source

NAND Flash memories

2008
NAND Flash memories are the storage media used inside Solid State Drives (SSDs). Indeed, a single drive for enterprise applications can contain up to hundreds of Flash chips. Flash memories are non-volatile in the sense that they can retain the information even when powered off, but they wear out, i.e.
R. Micheloni, A. Marelli, R. Ravasio
openaire   +1 more source

FTL algorithms for NAND-type flash memories

Design Automation for Embedded Systems, 2011
Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated ...
Se Jin Kwon   +3 more
openaire   +1 more source

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

IEEE International Solid-State Circuits Conference
3D-NAND Flash memory is evaluated as a key device that is handling the explosive data growth, showing steady bit growth and areal density increases >30% every year.
Won-Chang Jung   +53 more
semanticscholar   +1 more source

On-Chip Learning in Vertical NAND Flash Memory Using Forward–Forward Algorithm

IEEE Transactions on Electron Devices
Unlike the previous ON-chip learning using backward propagation (BP) in vertical NAND (V-NAND) flash memory, a new approach utilizing only forward propagation (FP) is proposed.
Sung-Ho Park   +8 more
semanticscholar   +1 more source

NAND Flash Memory and Its Place in IoT

Irish Signals and Systems Conference, 2021
Data storage requires an answer to the constantly evolving question - how best to store the mammoth amount of data being generated? There is a great diversity of storage solutions currently, ranging from personal USB devices, personal Solid State Drives (
Sorcha Bennett, Joseph P. Sullivan
semanticscholar   +1 more source

Fast booting based on nand flash memory

Proceedings of the 2012 ACM Research in Applied Computation Symposium, 2012
Fast booting is an important tool for minimizing the booting time of embedded systems, and a major factor in determining the usability of the systems. Most fast booting tools have focused on minimizing the booting time by optimizing the processing time from the starting stage of the boot loader to mounting stage of the root file system.
Yun Kyu Lee, Hyungbae Park, Cheol Jeon
openaire   +1 more source

Adaptive Differential Wearing for Read Performance Optimization on High-Density nand Flash Memory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
With cost reduction and density optimization, high-density NAND flash memory has been widely deployed in data centers and consumer devices. However, this trend has significantly degraded the read performance and lifetime of high-density NAND flash memory
Yunpeng Song, Yina Lv, Liang Shi
semanticscholar   +1 more source

Beyond 10 μm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A novel High-Aspect-Ratio (HAR) dielectric etch technology which is capable of etching beyond $10 \mu \mathrm{m}$ depth memory channel hole for future generations of 3D NAND flash memory has been successfully developed for the first time.
Y. Kihara   +4 more
semanticscholar   +1 more source

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