Results 171 to 180 of about 29,884 (210)

Characterizing 3D Floating Gate NAND Flash

Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2017
In this paper, we characterize a state-of-the-art 3D floating gate NAND flash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND flash-oriented designs can be developed
Qin Xiong, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, Ping Huang   +7 more
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Proposed time‐mode wide fan‐in NAND and NOR gates

International Journal of Circuit Theory and Applications, 2023
SummaryCMOS circuits usually operate either in the voltage, current, charge, or time domain. Each of these domains has its own features. As the fan‐in of CMOS circuits increases, the performance of circuits that operate in the voltage domain, the current domain, or the charge domain degrades.
Sherif M. Sharroush, Emad Badry
openaire   +1 more source

Heuristic unloading procedure for NAND and NOR gates

International Journal of Electronics, 1978
Properties of the transcription procedure related to logical functions build in NAND and NOR gates are used for an heuristic research of unloading. Tabulations are given in some practical cases.
D. DUBUS, A. J. TOSSER
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Optoelectronic NAND- and NOR-type logical gates

SPIE Proceedings, 2000
Optoelectronic logical gates NAND and NOR are composed of thin film photoconducting and electroluminescent elements, made of cadmium sulphide and zinc sulphide respectively, doped with copper, chlorine and manganese. These gates consist of several photoconducting elements and one electroluminescent element connected in series or parallel, supplied with
Zbigniew W. Porada, Elzbieta Schabowska-Osiowska   +1 more
openaire   +1 more source

NAND Gate Design for Ballistic Deflection Transistors

IEEE Transactions on Nanotechnology, 2009
This paper presents a nand gate designed using ballistic deflection transistors (BDTs). Room temperature BDT measurements are captured in an empirical device model to simulate multi-BDT logic design. Measurements from a fabricated BDT nand gate validate the multidevice model and demonstrate the promise of BDTs for nanoscale circuit design.
D. Wolpert, Q. Diduck, P. Ampadu
openaire   +1 more source

Another logical molecular NAND gate system

Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 2003
In this paper we implement a new logic NAND gate using standard operations on DNA strands as well as digestion by the restriction nuclease class II. This concept despite some difficulties looks in general more elegant and can be utilized with fluorescent probes.
J.J. Mulawka, P. Wasiewicz, A. Plucienniczak   +2 more
openaire   +1 more source

Performance Analysis of Single-electron NAND Gates

ECS Transactions, 2009
In this work, three different circuit architectures implementing single-electron NAND gates are investigated by simulation. A complete behavior analysis of each architecture, considering critical aspects in SET-based circuits, such as co-tunnelling, temperature dependence and offset charges is performed. Power consumption and area estimations (critical
Lorena Silva, Janaina G. Guimaraes
openaire   +1 more source

Metal control gate for sub-30nm floating gate NAND memory

2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS), 2008
This paper investigates the use of a metal control gate for sub 30 nm NAND flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the
N. Chan, M. F. Beug, R. Knoefler, T. Mueller, T. Melde, M. Ackermann, S. Riedel, M. Specht, C. Ludwig, A. T. Tilke   +9 more
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Design of AND logic gate using NAND gate in photonic crystal waveguides

SPIE Proceedings, 2016
In this paper, we have proposed the design of all-optical AND logic gate using the combination of universal NAND gates. The structure consists of hexagonal arrangement of air holes in silicon. The proposed structure has been designed using the finite difference time domain (FDTD) method. The optimized NAND gates have been arranged in a combination such
Shiba Fatima, Preeti Rani, Yogita Kalra, R. K. Sinha   +3 more
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A design of ternary logic circuits using M‐NAND and NOT gates

Systems and Computers in Japan, 1985
AbstractWe have proposed the canonical form for the p‐valued logical function (p is a natural number, p > 2), using M‐AND, M‐OR and NOT operations. However, the relations among those operations have been discussed only briefly. This paper discusses in detail the properties of M‐NAND, M‐OR and NOT operations for the ternary case (p = 3), deriving ...
Akio Odaka, Kunio Satoh
openaire   +1 more source