Results 1 to 10 of about 3,095,076 (264)

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su-Hwan Choi, Jae-min Sim, Jeongmin Shin, Seong-Hwan Ryu, Taewon Hwang, So-Young Lim, Hye-Jin Oh, Jae-Hyeok Kwag, Jun-Yeoub Lee, Ki-Cheol Song, Yeonhee Lee, Minju Song, Junghwan Kim, Chang-Kyun Park, Yun‐Heub Song, Jinsin Park   +15 more
semanticscholar   +1 more source

A Behavioral Compact Model of 3D NAND Flash Memory

CoRR, 2018
We present a behavioral compact model of 3D NAND flash memory for integrated circuits and system-level applications. This model is easy to implement, computationally efficient, fast, accurate and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap ...
Shubham Sahay, Dmitri B. Strukov
openaire   +2 more sources

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

ACM Transactions on Architecture and Code Optimization (TACO)
With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code,
Qiao Li, Yu Chen, Guanyu Wu, Yajuan Du, Min Ye, Xinbiao Gan, Jie Zhang, Zhirong Shen, Ji-Wu Shu, C. Xue   +9 more
semanticscholar   +1 more source

White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology

Journal of Microelectronic Manufacturing, 2019
In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of ...
Xiaoye Ding, Sicong Wang, Yi Zhou, Yanzhong Ma, Le Yang, Chi Chen   +5 more
doaj   +1 more source

Investigation of the Connection Schemes between Decks in 3D NAND Flash. [PDF]

Micromachines (Basel), 2023
Jia J, Jin L, You K, Zhu A.
europepmc   +1 more source

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory. [PDF]

Micromachines (Basel), 2023
You K, Jin L, Jia J, Huo Z.
europepmc   +1 more source

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

ACM Trans. Design Autom. Electr. Syst.
Considering 3D NAND flash has a new property of process variation (PV), which causes different raw bit error rates (RBER) among different layers of the flash block.
Huan Tian, Jiewen Tang, Jun Li, Zhibing Sha, Fan Yang, Zhigang Cai, Jianwei Liao   +6 more
semanticscholar   +1 more source

Optimizing Cell Structure to Improve Cell Characteristics in IGZO Channel-Based 3D NAND Flash With p-Type Gate

IEEE Access
For the first time, a novel IGZO channel-based 3D NAND Flash structure with an embedded p-type poly-Si injection layer is proposed, using integrated structural, material, and operational modifications to address the limitations of the conventional IGZO ...
Sungho Park, Youngho Jung, Daewoong Kang
doaj   +1 more source

Modeling methodology for thermo-structural analysis of V-NAND flash memory structure

Scientific Reports
This study proposes modeling methodology based on a continuous model for conducting thermo-electric-structural analyses of V-NAND flash memory structure under the Joule heating effect.
Yongha Kim, Seungjun Ryu, Sungryung Lee
doaj   +1 more source

Life-after-Death: Exploring Thermal Annealing Conditions to Enhance 3D NAND SSD Endurance

USENIX Workshop on Hot Topics in Storage and File Systems
In this paper, we evaluate thermal annealing effects on the endurance of commercial off-the-shelf (COTS) 3D NAND flash memory beyond its end-of-life. We systematically evaluate the effects of anneal duration, anneal temperature, and state of the memory ...
Matchima Buddhanoy, S. Pasricha, Biswajit Ray   +2 more
semanticscholar   +1 more source