Results 11 to 20 of about 209 (132)
IEEE Access, 2023 To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeats, problems such as electrons accumulation in the inter-cell region are occurred. To solve this problem, a method of
Yun-Jae Oh +4 more
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Nanomaterials, 2022 As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the
Xinyue Yu +6 more
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Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing
Journal of Microelectronic Manufacturing, 2020 3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a three-dimensional vertical structure with high-aspect ratio.
Wei Zhang +4 more
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Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages
Micromachines, 2022 Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated.
Dongwoo Lee, Changhwan Shin
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Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2020 Poly-Si channels need well passivated by using hydrogen passivation process in 3D NAND flash memories for better poly-Si quality with low trap density.
Xinshuai Shen +7 more
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Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang +4 more
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Impact of Cycling Induced Intercell Trapped Charge on Retention Charge Loss in 3-D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2020 As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics ...
Xinlei Jia +11 more
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A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2022 Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the
Zhichao Du +11 more
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Forensic Analysis of the Nintendo 3DS NAND
Digital Investigation, 2019 Abstract Games consoles present a particular challenge to the forensics investigator due to the nature of the hardware and the inaccessibility of the file system. Many protection measures are put in place to make it deliberately difficult to access raw data in order to protect intellectual property, enhance digital rights management of software and ...
Gus Pessolano +3 more
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Channel Modeling and Quantization Design for 3D NAND Flash Memory
Entropy, 2023 As the technology scales down, two-dimensional (2D) NAND flash memory has reached its bottleneck. Three-dimensional (3D) NAND flash memory was proposed to further increase the storage capacity by vertically stacking multiple layers.
Cheng Wang +5 more
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