Results 21 to 30 of about 2,680 (203)
Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next‐Generation High‐Density Storage Systems [PDF]
Multilevel storage and low‐voltage operation position ferroelectric transistors as promising candidates for next‐generation nonvolatile memory. Among them, gate‐injection‐type ferroelectric transistors offer improved vertical scalability and power ...
Giuk Kim +12 more
doaj +2 more sources
Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory [PDF]
In order to successfully achieve mass production in NAND flash memory, a novel test procedure has been proposed to electrically detect and screen the channel hole defects, such as Not-Open, Bowing, and Bending, which are unique in high-density 3D NAND ...
Beomjun Kim +2 more
doaj +2 more sources
Modeling methodology for thermo-structural analysis of V-NAND flash memory structure [PDF]
This study proposes modeling methodology based on a continuous model for conducting thermo-electric-structural analyses of V-NAND flash memory structure under the Joule heating effect.
Yongha Kim, Seungjun Ryu, Sungryung Lee
doaj +2 more sources
In flash memory technology, mechanical stress is considered as one of the major factors that can influence the device performance. Furthermore, mechanical stress can have a greater impact on the electrical performance in 3D NAND than in 2D NAND because ...
Eun-Kyeong Jang +4 more
doaj +1 more source
Analytical Modeling of 3D NAND Flash Cell With a Gaussian Doping Profile
The incessantly increasing demand for highly dense storage medium in this era of big-data has led to the development of 3D NAND Flash memories. 3D NAND Flash based SSDs have revolutionized edge storage and become an integral part of the data warehouses ...
Amit Kumar, Raushan Kumar, Shubham Sahay
doaj +1 more source
Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory
Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al., 2007, Lee et al., 2018,
Ting Cheng +13 more
doaj +1 more source
To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeats, problems such as electrons accumulation in the inter-cell region are occurred. To solve this problem, a method of
Yun-Jae Oh +4 more
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Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory [PDF]
3D NAND flash memory faces unprecedented complicated interference than planar NAND flash memory, resulting in more concern regarding reliability and performance. Stronger error correction code (ECC) and adaptive reading strategies are proposed to improve
Fei Wu +15 more
core +1 more source
Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing
3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a three-dimensional vertical structure with high-aspect ratio.
Wei Zhang +4 more
doaj +1 more source
Secondary Particles Generated by Protons in 3D NAND Flash Memories [PDF]
We studied the secondary byproducts created by high-energy protons inside an SEU detector based on 3D NAND Flash memories, extending the previously developed methodology used for detecting heavy ions.
Gerardin S. +8 more
core +1 more source

