Results 101 to 110 of about 49,281,268 (309)
Editorial for the Special Issue on Network on Chip (NoC) and Reconfigurable Systems. [PDF]
Zitouni A.
europepmc +1 more source
A reconfigurable logic‐in‐memory cell composed of triple‐gated feedback field‐effect transistors implements multiple combinational logic functions within a single configuration. By utilizing program gates as dynamic input terminals, the proposed cell performs full adder, full subtractor, 2‐to‐1 multiplexer, and 4‐to‐2 encoder operations without ...
Minhyeok Seol +5 more
wiley +1 more source
Serialization and asynchronous techniques for reliable network-on-chip communication
The Network-on-Chip (NoC) paradigm has been proposed as a potentially viable onchip communication infrastructure for multiprocessor SoC. This thesis investigates the development and validation of efficient links that improve NoC performance, power ...
Ogg, Simon
core
Numerical simulation of titanium alloy dry machining with a strain softening constitutive law [PDF]
In this study, the commercial finite element software FORGE2005, able to solve complex thermo-mechanical problems is used to model titanium alloy dry machining.
CALAMAZ, Madalina +5 more
core +1 more source
Network-on-chip (NoC) is an emerging alternative to address the communication problem in embedded system-on-chip designs. One of the key and major issues is the optimized mapping of the embedded applications on the underlined NoC platform. In this paper,
Sarzamin Khan +4 more
doaj +1 more source
Asynchronous design of networks-on-chip [PDF]
The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally-synchronous, mesochronous, globally-asynchronous locally ...
openaire +1 more source
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone +11 more
wiley +1 more source
An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture
Network-on-chip (NoC) has appeared to be an impending substitute for the communication paradigm in modern very large scale integration embedded systems.
Sarzamin Khan +5 more
doaj +1 more source
From Food to Power: Hydrogel Thermoelectrics for Ingestible Electronics
We introduce a fully edible thermoelectric–electrochromic platform that harvests heat from food and converts it into a visible color change. N‐type and p‐type hydrogel thermoelectric generators connected in series power anthocyanin‐based electrochromic displays, demonstrating the feasibility of safe, biodegradable, ingestible systems for on‐food ...
Antonia Georgopoulou +3 more
wiley +1 more source
Towards Open Network-on-Chip Benchmarks
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far.
Partha Pande +13 more
core +1 more source

