Results 101 to 110 of about 11,736 (210)

Novel NoC Topology Construction for High-Performance Communications

Journal of Computer Networks and Communications, 2011
Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects.
P. Ezhumalai, A. Chilambuchelvan, C. Arun   +2 more
doaj   +1 more source

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Journal of Low Power Electronics and Applications, 2017
The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology ...
Emmanuel Ofori-Attah, Washington Bhebhe, Michael Opoku Agyeman   +2 more
doaj   +1 more source

A study of recent contributions on simulation tools for Network-on-Chip (NoC) [PDF]

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements.
Opoku Agyeman, Michael, Saleh Alalaki, Muthana   +1 more
core  

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

International Journal of Reconfigurable Computing, 2012
This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system ...
Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner   +5 more
doaj   +1 more source

On Asymptotic Analysis of Packet and Wormhole Switched Routing Algorithm for Application-Specific Networks-on-Chip

Journal of Electrical and Computer Engineering, 2012
The application of the multistage interconnection networks (MINs) in systems-on-chip (SoC) and networks-on-chip (NoC) is hottest since year 2002. Nevertheless, nobody used them practically for parallel communication. However, to overcome all the previous
Nitin
doaj   +1 more source

A comprehensive study and holistic review of empowering network-on-chip application mapping through machine learning techniques

Discover Electronics
This study investigates machine learning (ML) techniques for optimizing Network-on-Chip (NoC) application mapping, focusing on supervised learning, unsupervised learning, reinforcement learning, and neural networks.
Yasin Asadi
doaj   +1 more source

OSDTM: an Offline-Structural Distributed Test Mechanism for Data Links in NoC

International Journal of Information and Communication Technology Research, 2018
The Micro Packet Switched based Network on Chip (NoC) is emerged to address traditional non-scalable buses-based Systems on Chip (SoC) challenges such as out of order transactions, flow control and higher latencies.
Babak Aghaei, Ahmad Khademzadeh, Kambiz Badie, Midia Reshadi, Saeid Sarhangi   +4 more
doaj  

HT-NoC: Reconfigurable High Throughput Network-on-Chip for AI Dataflow Accelerators

Fully Connected (FC) layers are a bottleneck for many DeepNeural Networks (DNN) algorithms due to their high bandwidth require-ments, which makes their hardware acceleration particularly challenging.In this paper, we address this challenge from a communication-centricapproach.
Mohamed Amine Zhiri, Hana Krichene, Chiara Sandionigi, Sébastien Pillement   +3 more
openaire   +2 more sources

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Iraqi Journal for Computer Science and Mathematics
Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms.
yousif muhsen, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Manshor, Ahmed Abbas Jasim Al-Hchaimi, A. S. Albahri   +5 more
doaj   +1 more source

Hybrid Optimization Algorithm Based on Double Particle Swarm in 3D NoC Mapping. [PDF]

Micromachines (Basel), 2023
Fang J, Cai H, Lv X.
europepmc   +1 more source