Results 121 to 130 of about 1,145 (180)

Spike-based dynamic computing with asynchronous sensing-computing neuromorphic chip. [PDF]

Nat Commun
Yao M, Richter O, Zhao G, Qiao N, Xing Y, Wang D, Hu T, Fang W, Demirci T, De Marchi M, Deng L, Yan T, Nielsen C, Sheik S, Wu C, Tian Y, Xu B, Li G.   +17 more
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A high level power model for Network-on-Chip (NoC) router

Computers and Electrical Engineering, 2009
This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstraction. Experimental results show that our power macro
Nader Bagherzadeh, Seung Eun Lee
exaly   +2 more sources

Versal Network-on-Chip (NoC)

2019 IEEE Symposium on High-Performance Interconnects (HOTI), 2019
Xilinx Versal Adaptable Compute Acceleration Platform (ACAP) is a new software-programmable heterogenous compute platform. The slowing of Moores law and the everpresent need for higher levels of compute performance has spurred the development of many domain specific accelerator architectures. ACAP devices are well suited to take advantage of this trend.
Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Bala Jayadev, Jeff Cuppett, Abbas Morshed, Brian Gaide, Ygal Arbel   +7 more
openaire   +1 more source

Interconnect intellectual property for Network-on-Chip (NoC)

Journal of Systems Architecture, 2004
As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation ...
Jian Liu, Li-Rong Zheng 0001, Hannu Tenhunen   +2 more
openaire   +1 more source

Malleable NoC: Dark Silicon Inspired Adaptable Network-on-Chip

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
Jörg Henkel, Muhammad Shafique, Sri Parameswaran   +2 more
exaly   +4 more sources

Networks-on-Chip (NoC)

2011
The move to many-core system is expected to become the dominant trend in the near future. With technology scaling into nanoscale regime, hundreds and even thousands of intellectual property (IP) cores can be integrated into a single chip. How to provide efficient and reliable communication between these IP cores becomes a bit problem.
Bo Fu, Paul Ampadu
openaire   +1 more source

NoC: Network or Chip?

First International Symposium on Networks-on-Chip (NOCS'07), 2007
Summary form only given. The concept of a communication network emerged, many times in the past, for connecting a large number of systems, replacing dedicated point-to-point connection and other small-scale interconnection mechanisms. Each network needs to provide a cost effective solution for a large number of possibly conflicting requirements such as
openaire   +1 more source

Secure Model Checkers for Network-on-Chip (NoC) Architectures

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations.
Travis Boraten, Dominic DiTomaso, Avinash Karanth Kodi   +2 more
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On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture

Fourth International Conference on Information Technology (ITNG'07), 2007
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algorithm even if basic network problems such as deadlock and livelock, are considered.
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh   +2 more
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Increasing the throughput of an adaptive router in network-on-chip (NoC)

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, 2006
In this paper, we propose a simple and efficient mechanism to increase the throughput of an adaptive router in Network-on-Chip (NoC). One of the most serious disadvantages of fully adaptive wormhole routers is its performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of different clocks in a head
Seung Eun Lee, Nader Bagherzadeh
openaire   +1 more source